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公开(公告)号：US20160315048A1
公开(公告)日：2016-10-27
申请号：US15138167
申请日：2016-04-25
Applicant: XINTEC INC.
Inventor： Yen-Shih HO , Shu-Ming CHANG , Hsing-Lung SHEN , Yu-Hao SU , Kuan-Jung WU , Yi CHENG
IPC: H01L23/522 , H01L23/48 , H01L21/768 , H01L21/288 , C25D17/08 , H01L49/02 , H01L21/673 , H01L21/677 , C25D17/00 , C25D7/12 , H01L27/144 , H01L21/3205
CPC classification number: H01L23/49838 , C25D17/001 , C25D17/005 , C25D17/06 , H01L21/2885 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/68721 , H01L21/76898 , H01L23/481 , H01L23/498 , H01L23/49811 , H01L23/49827 , H01L23/5227 , H01L23/525 , H01L23/53214 , H01L23/53228 , H01L28/10 , H01L2224/11
Abstract: A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.
Abstract translation: 半导体电镀系统包括导电环和至少一个导电装置。 导电环用于承载晶片。 导电环具有至少两个连接点。 晶片具有第一表面和相对的第二表面。 隔离层位于第二表面上。 导电装置的两端分别连接到导电环的两个连接点。 当导电环浸入电镀溶液中并通电时，在隔离层上形成待图案化的再分配层。 导电装置用于将通过其中一个连接点的部分电流传送到另一个连接点。
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公开(公告)号：US20240109769A1
公开(公告)日：2024-04-04
申请号：US18538503
申请日：2023-12-13
Applicant: Xintec Inc.
Inventor： Wei-Luen SUEN , Jiun-Yen LAI , Hsing-Lung SHEN , Tsang-Yu LIU
CPC classification number: B81B7/0067 , B81C1/00317 , B81B2203/0353 , B81C2201/0125 , B81C2201/0132 , B81C2201/0194
Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.
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公开(公告)号：US20200333542A1
公开(公告)日：2020-10-22
申请号：US16851099
申请日：2020-04-17
Applicant: XINTEC INC.
Inventor： Jiun-Yen LAI , Yu-Ting HUANG , Hsing-Lung SHEN , Tsang-Yu LIU , Hui-Hsien WU
IPC: G02B6/42
Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.
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公开(公告)号：US20210210538A1
公开(公告)日：2021-07-08
申请号：US17133636
申请日：2020-12-24
Applicant: XINTEC INC.
Inventor： Jiun-Yen LAI , Wei-Luen SUEN , Hsing-Lung SHEN , Yu-Ting HUANG
IPC: H01L27/146
Abstract: A chip package is provided. The chip package includes a first substrate and a second substrate disposed over the first substrate. The first substrate and the second substrate have a lower surface and an upper surface, and the second substrate includes a first recess region surrounding the second substrate. The first recess region has a tapered sidewall and a bottom surface that is between the lower and upper surfaces of the second substrate. The chip package also includes at least one conductive pad disposed on the upper surface of the second substrate and a redistribution layer (RDL) correspondingly disposed on the conductive pad. The RDL is extended from the conductive pad onto the bottom surface of the first recess region along the tapered sidewall of the first recess region. A method of forming a chip package is also provided.
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公开(公告)号：US20210104455A1
公开(公告)日：2021-04-08
申请号：US17037151
申请日：2020-09-29
Applicant: XINTEC INC.
Inventor： Wei-Luen SUEN , Jiun-Yen LAI , Hsing-Lung SHEN , Tsang-Yu LIU
IPC: H01L23/498 , H01L21/48
Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.
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Patent Agency Ranking
公开(公告)号：US20170207194A1
公开(公告)日：2017-07-20
申请号：US15409511
申请日：2017-01-18
Applicant: XINTEC INC.
Inventor： Hsing-Lung SHEN , Jiun-Yen LAI , Yu-Ting HUANG , Tsung-Cheng CHAN , Jan-Lian LIAO , Hung-Chang CHEN , Ming-Chieh HUANG , Hsi-Chien LIN
CPC classification number: H01L24/03 , H01L21/563 , H01L23/295 , H01L23/3128 , H01L23/3135 , H01L23/3171 , H01L23/3178 , H01L24/06 , H01L24/13 , H01L24/24 , H01L24/82 , H01L24/94 , H01L25/50 , H01L2224/02373 , H01L2224/13022 , H01L2224/13024 , H01L2224/24145 , H01L2224/82005 , H01L2224/94 , H01L2924/10253 , H01L2924/1433 , H01L2924/3511 , H01L2924/3512 , H01L2224/82
Abstract: A chip package is provided. The chip package includes a first chip including a carrier substrate and a device substrate thereon. A second chip is mounted on the device substrate. A portion of the device substrate extends outward from the edge of the second chip, so as to be exposed from the second chip. A conductive pad is between the device substrate and the second chip. A polymer protective layer conformally covers the second chip, the exposed portion of the device substrate, and the edge of the carrier substrate. A redistribution layer is disposed on the polymer protective layer and extends into a first opening that passes through the polymer protective layer and the second chip and exposes the conductive pad, so as to be electrically connected to the conductive pad.
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公开(公告)号：US20210269303A1
公开(公告)日：2021-09-02
申请号：US17184443
申请日：2021-02-24
Applicant: XINTEC INC.
Inventor： Wei-Luen SUEN , Jiun-Yen LAI , Hsing-Lung SHEN , Tsang-Yu LIU
Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.
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公开(公告)号：US20160322312A1
公开(公告)日：2016-11-03
申请号：US15140199
申请日：2016-04-27
Applicant: XINTEC INC.
Inventor： Hsing-Lung SHEN , Jiun-Yen LAI , Yu-Ting HUANG
CPC classification number: H01L23/564 , H01L21/561 , H01L21/76898 , H01L21/78 , H01L22/32 , H01L22/34 , H01L23/3114 , H01L23/3128 , H01L23/315 , H01L23/3178 , H01L23/3185 , H01L23/481 , H01L31/0203 , H01L31/02164 , H01L33/62 , H01L2224/11
Abstract: A chip package includes a chip, a dam layer, a carrier substrate and a light shielding passivation layer. The chip has a first surface and a second surface opposite to the first surface, and a side surface is disposed between the first surface and the second surface. The dam layer is disposed on the first surface, and the carrier substrate is disposed on the dam layer. The light shielding passivation layer is disposed under the second surface and extended into the carrier substrate to cover the side surface of the chip.
Abstract translation: 芯片封装包括芯片，阻挡层，载体基板和遮光钝化层。 芯片具有与第一表面相对的第一表面和第二表面，并且侧表面设置在第一表面和第二表面之间。 阻挡层设置在第一表面上，载体基板设置在阻挡层上。 遮光钝化层设置在第二表面下方并延伸到载体衬底中以覆盖芯片的侧表面。
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公开(公告)号：US20160315061A1
公开(公告)日：2016-10-27
申请号：US15091122
申请日：2016-04-05
Applicant: XINTEC INC.
Inventor： Yen-Shih HO , Shu-Ming CHANG , Hsing-Lung SHEN
CPC classification number: H01L24/17 , H01L21/4846 , H01L23/147 , H01L23/3121 , H01L23/3192 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/16 , H01L2224/02372 , H01L2224/0345 , H01L2224/0346 , H01L2224/0391 , H01L2224/0401 , H01L2224/05022 , H01L2224/05548 , H01L2224/05567 , H01L2224/0603 , H01L2224/06182 , H01L2224/08267 , H01L2224/08268 , H01L2224/13024 , H01L2224/131 , H01L2224/1403 , H01L2224/16112 , H01L2224/16145 , H01L2224/16267 , H01L2224/16268 , H01L2224/81191 , H01L2224/81192 , H01L2224/81815 , H01L2224/81986 , H01L2924/00014 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/11 , H01L2924/014
Abstract: A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.
Abstract translation: 芯片封装包括第一芯片和第二芯片。 第一芯片包括具有第一表面和与第一表面相对的第二表面的第一基板，第一表面上的第一无源元件和覆盖第一无源元件的第一保护层，第一保护层具有第三表面 与第一个表面相对。 第一和第二导电焊盘结构设置在第一保护层中并电连接到第一无源元件。 第二芯片设置在第三表面上，第二芯片包括有源元件和与有源元件电连接的第二无源元件。 有源元件电连接到第一导电焊盘结构。
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公开(公告)号：US20160315043A1
公开(公告)日：2016-10-27
申请号：US15138119
申请日：2016-04-25
Applicant: XINTEC INC.
Inventor： Yen-Shih HO , Shu-Ming CHANG , Hsing-Lung SHEN , Yu-Hao SU , Kuan-Jung WU , Yi CHENG
IPC: H01L23/498 , H01L21/687 , H01L49/02 , H01L21/48
CPC classification number: H01L23/49838 , C25D17/001 , C25D17/005 , C25D17/06 , H01L21/2885 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/68721 , H01L21/76898 , H01L23/481 , H01L23/498 , H01L23/49811 , H01L23/49827 , H01L23/5227 , H01L23/525 , H01L23/53214 , H01L23/53228 , H01L28/10 , H01L2224/11
Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.
Abstract translation: 芯片封装包括芯片，隔离层和再分配层。 芯片具有基板，电焊盘和保护层。 基板具有第一表面和第二表面。 基板具有通孔，保护层具有凹孔，使得电焊盘通过凹孔和通孔露出。 隔离层位于第二表面，通孔的侧壁和凹孔的侧壁上。 再分配层包括连接部分和无源元件部分。 连接部分位于隔离层上并与电焊垫电接触。 无源元件部分位于第二表面上的隔离层上，无源元件部分的一端连接到第二表面上的连接部分。
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