公开(公告)号：US20240242771A1

公开(公告)日：2024-07-18

申请号：US18407129

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer

IPC: G11C27/00

CPC classification number: G11C27/005

Abstract: Apparatuses, methods, and systems for using a subthreshold voltage for mapping in memory are disclosed. An example apparatus includes a memory array including a plurality of memory cells each programmable to a first data state or a second data state, and circuitry coupled to the memory array and configured to encode an input vector comprising a first number of data states to be programmed to a first group of memory cells of a memory array, apply a subthreshold voltage to each of a second group of memory cells of the memory array, wherein the second group of memory cells is programmed to a weight vector comprising a second number of data states and wherein the subthreshold voltage is based upon the data states of the input vector, and map the input vector to a location in the memory array using the weight vector after applying the subthreshold voltage.

公开(公告)号：US11996141B2

公开(公告)日：2024-05-28

申请号：US17716740

申请日：2022-04-08

Applicant: Micron Technology, Inc.

Inventor： Mattia Robustelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano

IPC: G11C11/56 ,  G11C7/10

CPC classification number: G11C11/56 ,  G11C7/1051 ,  G11C7/1096

Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

公开(公告)号：US20240029796A1

公开(公告)日：2024-01-25

申请号：US17868750

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Mattia Robustelli ,  Alessandro Sebastiani ,  Matteo Impala' ,  Fabio Pellizzer

IPC: G11C16/10 ,  G11C16/20 ,  G11C16/04

CPC classification number: G11C16/102 ,  G11C16/20 ,  G11C16/0425

Abstract: Systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. A memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. The current is a set pulse or a reset pulse. The set pulse and the reset pulse have a same polarity.

公开(公告)号：US11869577B2

公开(公告)日：2024-01-09

申请号：US18100802

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Enrico Varesi ,  Lorenzo Fratin ,  Fabio Pellizzer

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/4074

CPC classification number: G11C11/4085 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4087

Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

公开(公告)号：US20230395128A1

公开(公告)日：2023-12-07

申请号：US17830042

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Paolo Fantini

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/06

CPC classification number: G11C11/4087 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/063

Abstract: Methods, systems, and devices for decoder architectures for three-dimensional memory devices are described. In some cases, a decoder for a memory device may include two portions. A first portion of the decoder may be manufactured on top of the memory array, and may include a pillar decoding portion to selectively bias a first array of decoding elements coupled with conductive pillars of the memory array and a word line decoding portion to selectively bias a second array of decoding elements coupled with word lines of the memory array. A second portion of the decoder may be implemented in a separate semiconductor device which may include a set of logic circuits configured to drive signal to a set of contacts bonded to contacts of the first portion to drive the digit lines, voltage sources, and gate lines.

公开(公告)号：US11696454B2

公开(公告)日：2023-07-04

申请号：US17306444

申请日：2021-05-03

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Russell L. Meyer ,  Agostino Pirovano ,  Lorenzo Fratin

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/823 ,  H10N70/841 ,  H10N70/8828 ,  G11C13/0004 ,  G11C2213/71

Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

公开(公告)号：US11587635B2

公开(公告)日：2023-02-21

申请号：US17013089

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Nevil N. Gajera ,  Mingdong Cui ,  Fabio Pellizzer

IPC: G11C29/38 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.

公开(公告)号：US11587606B2

公开(公告)日：2023-02-21

申请号：US17231657

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Enrico Varesi ,  Lorenzo Fratin ,  Fabio Pellizzer

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/4074

Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

公开(公告)号：US20230029529A1

公开(公告)日：2023-02-02

申请号：US17937094

申请日：2022-09-30

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.

公开(公告)号：US20220359005A1

公开(公告)日：2022-11-10

申请号：US17869649

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C29/50 ,  G11C11/4074 ,  G11C11/409

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.