公开(公告)号：US09985035B1

公开(公告)日：2018-05-29

申请号：US15820455

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10885 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory structure includes a substrate including a memory cell region and a cell edge region adjacent to the memory cell region. Active regions are formed in the substrate and in the memory cell region and the cell edge region. At least a dummy bit line is formed on the active regions in the cell edge region. The dummy bit line extends along a first direction and overlaps at least two active regions along a second direction. The dummy bit line further includes a first inner line portion and an outer line portion. The first inner line portion and the outer line portion extend along the first direction and a width of the first inner line portion is different from a width of the outer line portion.

公开(公告)号：US09978873B2

公开(公告)日：2018-05-22

申请号：US15834070

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the STI not covered by the gate structure are etched, until the STI is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.

公开(公告)号：US20180138180A1

公开(公告)日：2018-05-17

申请号：US15802472

申请日：2017-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/225 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/2256 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823892 ,  H01L27/0886 ,  H01L29/66803

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.

公开(公告)号：US20180097098A1

公开(公告)日：2018-04-05

申请号：US15834070

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the STI not covered by the gate structure are etched, until the STI is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.

公开(公告)号：US20180061752A1

公开(公告)日：2018-03-01

申请号：US15271221

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Huang ,  Ching-Li Yang ,  Yu-Cheng Tung ,  Yu-Tsung Lai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/53295 ,  H01L28/60

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a capacitor is formed on the substrate and a hard mask on the capacitor, in which the capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. Next, a protective layer is formed on the sidewalls of the top electrode and the bottom electrode, in which the protective layer includes metal oxide.

公开(公告)号：US20180047635A1

公开(公告)日：2018-02-15

申请号：US15264590

申请日：2016-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.

公开(公告)号：US09859283B1

公开(公告)日：2018-01-02

申请号：US15479290

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10885 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory structure includes a substrate including a memory cell region, a peripheral circuit region and a cell edge region defined thereon, and the cell edge region is defined in between the memory cell region and the peripheral circuit region. The semiconductor memory structure includes a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region, and at least a dummy bit line formed on the active regions in the cell edge region. The dummy bit line is extended along a first direction and overlaps at least two active regions in a second direction. And the first direction and the second direction are perpendicular to each other. The dummy bit line includes a first inner line portion and an outer line portion, and the first inner line portion and the outer line portion include different widths and different spacers.

公开(公告)号：US09780169B2

公开(公告)日：2017-10-03

申请号：US14876844

申请日：2015-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Yu-Cheng Tung ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.

公开(公告)号：US09773860B1

公开(公告)日：2017-09-26

申请号：US15257930

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Tsung Lai ,  Ching-Li Yang ,  Yu-Cheng Tung ,  Shih-Che Huang ,  Chih-Sheng Chang

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: A method for fabricating a capacitor is disclosed. First, a substrate is provided, a bottom electrode and a capacitor dielectric layer are formed on the substrate, a conductive layer is formed on the capacitor dielectric layer, a patterned hard mask is formed on the conductive layer, a patterned hard mask is used to remove part of the conductive layer to form a top electrode, the patterned hard mask is removed, and a protective layer is formed on a top surface and sidewalls of top electrode. Preferably, the protective layer includes metal oxides.

公开(公告)号：US20170178716A1

公开(公告)日：2017-06-22

申请号：US15448599

申请日：2017-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: G11C11/417 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.