公开(公告)号：US20030231533A1

公开(公告)日：2003-12-18

申请号：US10460293

申请日：2003-06-11

Inventor： Takayuki Honda

IPC: G11C007/00

CPC classification number: H05K1/0216 ,  G11B20/24 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K2203/1572

Abstract: In a circuit board including an analog circuit and a digital circuit, the S/N ratio reduction resulting from the interference of digital signals with analog signals is suppressed. The circuit board includes a digital signal processing section forming part of the digital circuit, digital signal external conductors connected to the digital signal processing section, and digital signal output control means for interrupting the transmission of the digital signals from the digital signal processing section to the digital signal external conductors. A decrease in the limitation for the wiring pattern and the device arrangement provides an increase in the degree of freedom for designing, thereby making it possible to miniaturize the circuit board and to reduce the manufacturing cost thereof.

Abstract translation: 在包括模拟电路和数字电路的电路板中，由数字信号与模拟信号的干扰产生的S / N比减小被抑制。 电路板包括形成数字电路的一部分的数字信号处理部分，连接到数字信号处理部分的数字信号外部导体和用于中断数字信号从数字信号处理部分传输到数字信号处理部分的数字信号输出控制装置 数字信号外部导线。 布线图案和装置布置的限制的减少提高了设计的自由度，从而使得可以使电路板小型化并降低其制造成本。

公开(公告)号：US20030099190A1

公开(公告)日：2003-05-29

申请号：US09993138

申请日：2001-11-16

Inventor： Jared L. Zerbe

IPC: H04L001/20 ,  H04J015/00

CPC classification number: H04B3/32 ,  H01R13/6467 ,  H05K1/0228 ,  H05K2201/09245 ,  H05K2201/10689

Abstract: Described herein is a technique for reducing the effects of crosstalk between adjacent signal lines of a data path. The data path is formed by multiple signal lines arranged adjacent each other and traversing multiple segments. The signal lines are transposed between segments in a manner that is chosen to reduce differences in interline couplings between different pairs of the signal lines. The interline coupling of a pair of signal lines is represented as a function of coupling terms. A coupling term corresponds to each segment of a pair of signal lines, and is a function of the distance between the signal lines over that segment. Prior to transmitting a digital signal over the data path, the digital signal is encoded to reduce variations over time in a collective signal level of the digital signal.

Abstract translation: 这里描述了一种用于减少数据路径的相邻信号线之间串扰的影响的技术。 数据路径由彼此相邻布置并遍历多个段的多个信号线形成。 信号线以选择以减少不同对的信号线之间的线间耦合的差异的方式在段之间转置。 一对信号线的线间耦合表示为耦合项的函数。 耦合项对应于一对信号线的每个段，并且是该段上的信号线之间的距离的函数。 在通过数据路径发送数字信号之前，数字信号被编码以减少数字信号的集体信号电平中随时间的变化。

公开(公告)号：US06507495B1

公开(公告)日：2003-01-14

申请号：US09605448

申请日：2000-06-28

Applicant: Jeffery C. Hailey ,  Donald L. Brooks

Inventor： Jeffery C. Hailey ,  Donald L. Brooks

IPC: H05K702

CPC classification number: H05K1/0216 ,  H05K1/0239 ,  H05K1/162 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09663

Abstract: An apparatus for use with data processing systems. In one embodiment, the apparatus includes but is not limited to at least one conductive member having a first end electrically coupled to a first conductive structure which partially forms a moat and a second end electrically coupled to a second conductive structure which substantially spans the moat, with the second conductive structure having at least a part overhanging a third conductive structure which partially forms the moat. In one embodiment, the apparatus includes but is not limited to a first conductive member having a first end electrically coupled to a first conductive structure which partially forms a moat and a second end electrically coupled to a second conductive structure which substantially spans the moat, with the second conductive structure having at least a part overhanging a third conductive structure which partially forms the moat, and a second conductive member having a first end electrically coupled to the third conductive structure which partially forms the moat and a second end electrically coupled to a fourth conductive structure which substantially spans the moat, with the fourth conductive structure having at least a part overhanging the first conductive structure which partially forms the moat.

Abstract translation: 一种与数据处理系统一起使用的设备。 在一个实施例中，该装置包括但不限于至少一个导电构件，该导电构件具有电耦合到部分形成护城河的第一导电结构的第一端和与实质上跨越护城河的第二导电结构电耦合的第二端， 其中第二导电结构具有至少部分突出部分形成护城河的第三导电结构的部分。 在一个实施例中，该装置包括但不限于第一导电构件，该第一导电构件具有电耦合到部分形成护城河的第一导电结构的第一端和与基本跨越护城河的第二导电结构电耦合的第二端， 所述第二导电结构具有至少部分突出部分形成所述护城河的第三导电结构的部分，以及第二导电构件，所述第二导电构件具有电耦合到所述第三导电结构的第一端，所述第一导电结构部分地形成所述护城河， 导电结构，其基本上跨越护城河，其中第四导电结构具有至少部分突出部分形成护城河的第一导电结构的部分。

公开(公告)号：US20020176236A1

公开(公告)日：2002-11-28

申请号：US10142203

申请日：2002-05-10

Applicant: FUJI XEROX CO., LTD.

Inventor： Daisuke Iguchi ,  Joji Wakita ,  Kazumi Ikeda ,  Osamu Ueno

IPC: H05K005/00 ,  H05K005/04 ,  H05K005/06

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K9/0039 ,  H05K2201/09245 ,  H05K2201/09254 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/10689

Abstract: A printed wiring board is provided which can be applied even to circuit boards operating at high speed, and which can suppress electromagnetic wave radiation, and which can suppress a deterioration in density of mounting. At the printed wiring board, a first signal wire layer, a first ground layer having a first power source wire, a second ground layer having a second power source wire, and a second signal wire layer, are laminated. The first ground layer and the second ground layer are interlayer-connected by many via holes. Return current, of signal current flowing through a signal wire, flows in the first ground layer, and a path of the return current is cut midway therealong at a position of the first power source wire. However, the return current is detoured by the via hole to the second ground layer, and flows thereat.

Abstract translation: 提供了一种印刷电路板，其可以甚至应用于高速操作的电路板，并且可以抑制电磁波辐射，并且可以抑制安装密度的劣化。 在印刷电路板上层叠有第一信号线层，具有第一电源线的第一接地层，具有第二电源线的第二接地层和第二信号线层。 第一接地层和第二接地层通过许多通孔进行层间连接。 流过信号线的信号电流的返回电流在第一接地层中流动，并且在第一电源线的位置处，中途返回电流的路径被切断。 然而，返回电流被通孔旋转到第二接地层，并在那里流动。

公开(公告)号：US06429752B1

公开(公告)日：2002-08-06

申请号：US09597990

申请日：2000-06-19

Applicant: Thomas Harju ,  Thomas Emanuelsson

Inventor： Thomas Harju ,  Thomas Emanuelsson

IPC: H01P308

CPC classification number: H01P3/081 ,  H05K1/0251 ,  H05K1/0298 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09672 ,  H05K2201/09845

Abstract: The invention relates to an electrical transmission arrangement comprising a first section of a conductor with a main extension in two planes, and a first section of a ground plane which extends essentially in parallel with the conductor section on the first side of the conductor section and has a main extension in the same two planes as the conductor section. The transmission arrangement also comprises at least one second and one third section of the said conductor, which have their main extensions in the same two planes as the first section of the conductor, the second conductor section being displaced in parallel with respect to the first conductor section, and the third conductor section being displaced in parallel with respect to the second conductor section, and at least one second and one third section of the said ground plane, which have their main extensions in the same two planes as the first section of the ground plane, the second ground plane section being displaced in parallel with respect to the first ground plane section, and the third ground plane section being displaced in parallel with respect to the second ground plane section, the said parallel displacements of conductor sections and ground plane sections being done in a direction which is at right angles to the two planes which define the main extensions of the conductor sections and ground plane sections, each conductor section being electrically connected at least to the closest of the second conductor sections, each ground plane section being electrically connected at least to the closest of the second ground plane sections on the same side of the conductor, and the conductor sections being separated from the ground plane section by a dielectric material.

Abstract translation: 本发明涉及一种电传输装置，其包括在两个平面中具有主延伸的导体的第一部分和接地平面的第一部分，其基本上平行于导体部分的第一侧上的导体部分延伸，并且具有 在与导体部分相同的两个平面中的主要延伸。 所述传输装置还包括所述导体的至少一个第二和第三部分，它们的主要延伸部分与导体的第一部分相同的两个平面中，第二导体部分相对于第一导体平行移位 并且所述第三导体部分相对于所述第二导体部分并行移位，以及所述接地平面的至少一个第二和第三部分，所述第二导体部分的主要延伸部分在与所述第二部分的第一部分相同的两个平面中 所述第二接地平面部分相对于所述第一接地平面部分平行移位，并且所述第三接地平面部分相对于所述第二接地平面部分平行移位，所述平行位移的导体部分和接地平面 部分在与限定导体的主延伸部的两个平面成直角的方向上进行 每个导体部分至少与最靠近第二导体部分的电连接，每个接地平面部分至少与导体同一侧上最靠近的第二接地平面部分电连接，以及 导体部分通过电介质材料与接地平面部分分离。

公开(公告)号：US06423909B1

公开(公告)日：2002-07-23

申请号：US09795603

申请日：2001-02-27

Applicant: Carl R. Haynie ,  David Dickey ,  James J. deBlanc

Inventor： Carl R. Haynie ,  David Dickey ,  James J. deBlanc

IPC: H01R1204

CPC classification number: H05K1/0228 ,  H01R12/712 ,  H05K1/115 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09709 ,  H05K2201/10189

Abstract: A circuit board including differential bus traces on or buried within both sides of the board, interconnecting electronic devices such as disk drives, processors, and connectors for external cables. Via fields, which mimic the size and configuration of the device and cable connector fields, are located between each connector on the board. The via fields link bus traces on or within one side of the board with respective bus traces on or within the other side of the board. The via fields may include subtle, unequal undulations in the trace patterns to provide equalization in the lengths of all trace pairs. The via fields and the connector fields both include repetitive conductor order reversals in the trace connections on opposing sides of the board, to reduce crosstalk between channels. The via fields may be oriented parallel with respect to collinearly arranged devices, or orthogonal with respect to devices or connectors which are parallel. Where a connector has laterally offset groups of pin connections, a via field may also include offset groups of vias to provide trace length equalization.

Abstract translation: 电路板包括位于板的两侧或掩埋在板的两侧的差分总线迹线，互连电子设备，例如磁盘驱动器，处理器和用于外部电缆的连接器。 通过字段，模拟设备和电缆连接器字段的大小和配置，位于板上的每个连接器之间。 通孔区域将板的一侧上或其一侧的总线走线与板上另一侧的相应总线迹线相连。 通路区域可以包括迹线图案中微妙的，不相等的波动，以提供所有迹线对的长度的均衡。 通孔区域和连接器区域都包括在板的相对侧上的迹线连接中的重复导体顺序反转，以减少通道之间的串扰。 通孔区域可以相对于共线布置的器件取向平行，或者相对于平行的器件或连接器正交。 在连接器具有横向偏移销连接组的位置上，通孔区域还可以包括通孔的偏移组，以提供迹线长度均衡。

公开(公告)号：US06349038B1

公开(公告)日：2002-02-19

申请号：US09400025

申请日：1999-09-21

Applicant: Jeffery C. Hailey

Inventor： Jeffery C. Hailey

IPC: H05K111

CPC classification number: H05K1/0216 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09663

Abstract: An apparatus for use with data processing systems. The apparatus provides a split metallic conducting plane having a split formed by a substantially-dielectric-filled moat spanning a width of a side of a first metallic conducting part running substantially parallel to a side of a second metallic conducting part, with the moat structured such that the side of the first metallic part has at least two indentations and such that the side of the second metallic part has at least two indentations, and where a metallic trace is located proximate to the split metallic conducting plane.

Abstract translation: 一种与数据处理系统一起使用的设备。 该装置提供了一种裂开的金属导电平面，其具有由基本上介电填充的护城河形成的裂缝，跨越宽度基本上平行于第二金属导电部分的一侧延伸的第一金属导电部分的宽度， 第一金属部件的侧面具有至少两个压痕，并且使得第二金属部件的侧面具有至少两个压痕，并且其中金属迹线位于分开的金属导电平面附近。

公开(公告)号：US20020012240A1

公开(公告)日：2002-01-31

申请号：US09400025

申请日：1999-09-21

Inventor： JEFFERY C. HAILEY

IPC: H05K009/00 ,  H04B003/32

CPC classification number: H05K1/0216 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09663

Abstract: An apparatus for use with data processing systems. The apparatus provides a split metallic conducting plane having a split formed by a substantially-dielectric-filled moat spanning a width of a side of a first metallic conducting part running substantially parallel to a side of a second metallic conducting part, with the moat structured such that the side of the first metallic part has at least two indentations and such that the side of the second metallic part has at least two indentations, and where a metallic trace is located proximate to the split metallic conducting plane.

Abstract translation: 一种与数据处理系统一起使用的设备。 该装置提供了一种裂开的金属导电平面，其具有由基本上介电填充的护城河形成的裂缝，跨越宽度基本上平行于第二金属导电部分的一侧延伸的第一金属导电部分的宽度， 第一金属部件的侧面具有至少两个压痕，并且使得第二金属部件的侧面具有至少两个压痕，并且其中金属迹线位于分开的金属导电平面附近。

公开(公告)号：US5914644A

公开(公告)日：1999-06-22

申请号：US49259

申请日：1998-03-27

Applicant: Galen L. Carter ,  David A. Norte ,  Woong K. Yoon

Inventor： Galen L. Carter ,  David A. Norte ,  Woong K. Yoon

IPC: H05K9/00 ,  H01F17/00 ,  H01F17/06 ,  H03H1/00 ,  H05K1/02 ,  H05K1/16 ,  H05K1/18 ,  H05K3/22 ,  H03H7/09 ,  H04B3/28

CPC classification number: H03H1/0007 ,  H01F17/0006 ,  H01F17/06 ,  H05K1/0233 ,  H01F2017/065 ,  H05K1/0237 ,  H05K1/165 ,  H05K1/182 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K3/222

Abstract: A printed circuit (PC) board-mountable ferrite electromagnetic interference (EMI) filter (702, 1003, 1003") for PC conductors (701, 1001, 1002) of a printed circuit (PC) board (700, 1000) that accommodates large numbers of PC conductors, and is cost-effective. One embodiment of the EMI filter is used with a PC board (700) that routes PC conductors (701) in a step-function (i.e., a "U"-shaped) pattern. The EMI filter comprises a ferrite body (702) that defines two parallel passageways (708, 709), i.e., has a figure-8 shape in cross section. The portion (710) of the PC board that defines the PC conductor portions extending in the one direction lies in one passageway, whereas the portion (711) of the PC board that defines the PC conductor portions extending in the other direction lies in the other passageway. A different embodiment of the EMI filter is used with a PC board (1000) that routes sets (1001, 1002) of PC conductors in a cross-hatch (i.e., a "#"-shaped) pattern, where the PC conductors end (are interrupted) before intersecting so that each PC conductor comprises two separate straight on-board parts. This EMI filter comprises a ferrite body (1003) that defines two orthogonal sets (1012, 1013) of off-board "U"-shaped conductors, one set for each orthogonal set of PC conductors with one conductor of a set for each PC conductor of a set. Each PC conductor's corresponding "U"-shaped conductor interconnects the two straight on-board parts of the PC conductor.

Abstract translation: 一种印刷电路（PC）板（700,1000）的PC导体（701,1001,1002）的印刷电路（PC）板上安装的铁氧体电磁干扰（EMI）滤波器（702,1003,1003“），它们容纳 大量的PC导体，具有成本效益。 EMI滤波器的一个实施例与PC板（700）一起使用，PC板（700）以步进功能（即，“U”形））图案路由PC导体（701）。 EMI滤波器包括限定两个平行通道（708,709）的铁氧体本体（702），即横截面具有图形8形状。 限定沿一个方向延伸的PC导体部分的PC板的部分（710）位于一个通道中，而限定沿另一方向延伸的PC导体部分的PC板的部分（711）位于另一个 通道。 EMI滤波器的不同实施例与PC板（1000）一起使用，PC板（1000）以跨导线（即，“＃”形））模式传送PC导体的组（1001,1002），其中PC导体端 在相交之前被中断，使得每个PC导体包括两个单独的直的板上部件。 该EMI滤波器包括铁氧体本体（1003），其限定了板外“U”形导体的两个正交组（1012,1013），一组用于每个PC导体的正交组，每个PC导体具有一组导体 一套。 每个PC导体的相应的“U”型导体将PC导体的两个直线板载部分互连。

公开(公告)号：US5801597A

公开(公告)日：1998-09-01

申请号：US795431

申请日：1997-02-05

Applicant: Galen L. Carter ,  David A. Norte ,  Woong K. Yoon

Inventor： Galen L. Carter ,  David A. Norte ,  Woong K. Yoon

IPC: H05K9/00 ,  H01F17/00 ,  H01F17/06 ,  H03H1/00 ,  H05K1/02 ,  H05K1/16 ,  H05K1/18 ,  H05K3/22 ,  H03H7/09 ,  H04B3/28

CPC classification number: H03H1/0007 ,  H01F17/0006 ,  H01F17/06 ,  H05K1/0233 ,  H01F2017/065 ,  H05K1/0237 ,  H05K1/165 ,  H05K1/182 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K3/222

Abstract: A printed circuit (PC) board-mountable ferrite electromagnetic interference (EMI) filter (702, 1003, 1003") for striplines (701, 1001, 1002) of a printed circuit (PC) board (700, 1000) that accommodates large numbers of striplines, and is cost-effective. One embodiment of the EMI filter is used with a PC board (700) that routes striplines (701) in a step-function (i.e., a "U"-shaped) pattern. The EMI filter comprises a ferrite body (702) that defines two parallel passageways (708, 709), i.e., has a figure-8 shape in cross section. The portion (710) of the PC board that defines the stripline portions extending in the one direction lies in one passageway, whereas the portion (711) of the PC board that defines the stripline portions extending in the other direction lies in the other passageway. A different embodiment of the EMI filter is used with a PC board (1000) that routes sets (1001, 1002) of striplines in a cross-hatch (i.e., a "#"-shaped) pattern, where the striplines end (are interrupted) before intersecting so that each stripline comprises two separate straight on-board parts. This EMI filter comprises a ferrite body (1003) that defines two orthogonal sets (1012, 1013) of off-board "U"-shaped conductors, one set for each orthogonal set of striplines with one conductor of a set for each stripline of a set. Each stripline's corresponding "U"-shaped conductor interconnects the two straight on-board parts of the stripline.

Abstract translation: 一种用于适应大型印刷电路板（700,1000）的带状线（701,1001,1002）的印刷电路（PC）板上安装的铁氧体电磁干扰（EMI）滤波器（702,1003,1003“） 数量有条纹，并且具有成本效益。 EMI滤波器的一个实施例用于以步进功能（即，“U”形））图案路由带状线（701）的PC板（700）。 EMI滤波器包括限定两个平行通道（708,709）的铁氧体本体（702），即横截面具有图形8形状。 限定沿一个方向延伸的带状线部分的PC板的部分（710）位于一个通道中，而限定沿另一方向延伸的带状线部分的PC板的部分（711）位于另一个通道中。 EMI滤波器的不同实施例与PC板（1000）一起使用，PCB板（1000）以交叉影线（即，“＃”形））图案来对路线的集合（1001,1002）进行路由，其中​​带状线结束（被中断 ），使得每个带状线包括两个分开的直的板上部件。 该EMI滤波器包括铁氧体本体（1003），其限定了板外“U”形导体的两个正交组（1012,1013），一组用于每个正交的带状线集合，其中每个带状线的一个导体为 组。 每条带状线相应的“U”型导体将带状线的两个直线板载部分互连。