公开(公告)号：US20250006645A1

公开(公告)日：2025-01-02

申请号：US18343892

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Xiao Liu ,  Bohan Shan ,  Dingying Xu ,  Gang Duan ,  Haobo Chen ,  Hongxia Feng ,  Jung Kyu Han ,  Xiaoying Guo ,  Zhixin Xie ,  Xiyu Hu ,  Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Changhua Liu ,  Yosuke Kanaoka

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/58 ,  H01L25/10

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

公开(公告)号：US20250006630A1

公开(公告)日：2025-01-02

申请号：US18342130

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Thomas Wagner ,  Georg Seidemann ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.

公开(公告)号：US20250006623A1

公开(公告)日：2025-01-02

申请号：US18217056

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Shuqi Lai ,  Jieying Kong ,  Dilan Seneviratne ,  Whitney Bryks

IPC: H01L23/498

Abstract: Microelectronic integrated circuit package structures include one or more integrated circuit (IC) package metallization levels comprising metallization features. A dielectric material is adjacent to one or more of the metallization features, where the dielectric material comprises a matrix material and a surfactant. A plurality of substantially spherical pores are within the matrix material, where the substantially spherical pores are surrounded by an outer shell comprising the matrix material.

公开(公告)号：US20250006571A1

公开(公告)日：2025-01-02

申请号：US18883861

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Minglu Liu ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L23/15 ,  H01L23/538

Abstract: Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including thin film capacitors are disclosed. An example substrate includes a first glass layer, a dielectric layer on the first glass layer, a second glass layer, the first glass layer between the dielectric layer and the second glass layer, and a capacitor in the layer.

公开(公告)号：US20250006569A1

公开(公告)日：2025-01-02

申请号：US18883759

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Minglu Liu ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L23/15 ,  H01L23/24 ,  H01L23/367 ,  H01L23/538

Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer having a second CTE, the second CTE different from the first CTE.

公开(公告)号：US20250006434A1

公开(公告)日：2025-01-02

申请号：US18883126

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H10B12/00

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

公开(公告)号：US20250006139A1

公开(公告)日：2025-01-02

申请号：US18217495

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Susanta BHATTACHARJEE ,  Mohafiz Ulla KHAN ,  Greeshma VK ,  Ashish ROY

IPC: G09G3/34

Abstract: A system that includes at least one processor that is to execute a software to: determine pixel value adjustments based on a limit on contrast loss and to reduce power consumption of a display connected to the display interface and provide the pixel value adjustments to the display interface to apply to pixels of a video frame.

公开(公告)号：US20250006102A1

公开(公告)日：2025-01-02

申请号：US18343392

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Susanta Bhattacharjee ,  Kunjal Parikh

IPC: G09G3/20 ,  G09G3/3208

Abstract: A device, including: processing circuitry operable to determine boosted subpixel values for subpixels in a camera under display (CUD) area of a display panel, wherein each boosted subpixel value is based on a ratio of a non-CUD subpixel aperture area to a CUD subpixel aperture area for a corresponding subpixel of the display panel; and a display driver operable to boost a brightness of each subpixel in the CUD area based on the respective boosted subpixel value.

公开(公告)号：US20250005891A1

公开(公告)日：2025-01-02

申请号：US18343255

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Mallari C. Hanchate ,  Bharatkumar Mahajan ,  Manisha Raiguru ,  Krishna Kishore Nidamanuri

IPC: G06V10/60 ,  G06T5/00 ,  G06V10/25 ,  G09G3/3208

Abstract: Various embodiments herein provide apparatuses, systems, and methods associated with a region-based power saving scheme for a display, such as an organic light-emitting diode (OLED) display. In embodiments, pixels of an image may be allocated to two or more subsets including a first subset that corresponds to a region of interest (ROI). The two or more subsets may further include a second subset that includes some or all of the pixels that are outside of the ROI. A more aggressive power saving scheme may be applied to the second subset compared with the first subset (which may or may not undergo a power saving scheme). In some embodiments, a saturation level of the pixels of the second subset may be increased in addition to the dimming. Other embodiments may be described and claimed.

公开(公告)号：US20250005703A1

公开(公告)日：2025-01-02

申请号：US18773094

申请日：2024-07-15

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC: G06T1/20 ,  G06F3/14 ,  G06F9/30 ,  G06F9/38 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06T15/00 ,  G06T15/04 ,  G09G5/36

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.