公开(公告)号：US20250028611A1

公开(公告)日：2025-01-23

申请号：US18762217

申请日：2024-07-02

Applicant: Micron Technology, Inc.

Inventor： John M. Groves

IPC: G06F11/14

Abstract: A system can include a memory device and a processing device operatively coupled with the memory device, to perform operations of maintaining a set of data items reflective of a state of a host application and receiving a first request to make a checkpoint copy of the state of the host application. The operations can also include responsive to receiving the first request, associating a snapshot identifier with the object identifier, and receiving a second request to modify a data item of the set of data items at the first set of physical address ranges. They can also include executing the second request by recording a modification a data item exclusively at a second set of physical address ranges and making the checkpoint copy by copying the set of data items of the snapshot from the first set of physical address ranges to a second memory device.

公开(公告)号：US20250028595A1

公开(公告)日：2025-01-23

申请号：US18773151

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Eyal En Gad ,  Leonid Minz ,  Sivagnanam Parthasarathy

IPC: G06F11/10

Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.

公开(公告)号：US20250025117A1

公开(公告)日：2025-01-23

申请号：US18909407

申请日：2024-10-08

Applicant: Micron Technology, Inc.

Inventor： Yashvi SINGH ,  Tanya KHATRI ,  Fatma Arzum SIMSEK-EGE ,  Yanni WANG

IPC: A61B6/00 ,  A61B6/46

Abstract: In some implementations, a device may produce, via an x-ray module, x-rays to be directed towards a body part. The device may detect, via a sensor, the x-rays reflected from the body part. The device may generate, via the sensor, signals based on the x-rays reflected from the body part. The device may generate, via a processor, an x-ray image of the body part based on the first signals. The device may transmit the x-ray image to a server. The device may receive, from the server, a message that indicates a diagnosis associated with the x-ray image. The device may display, via a user interface, the x-ray image and information associated with the diagnosis associated with the x-ray image.

公开(公告)号：US12205641B2

公开(公告)日：2025-01-21

申请号：US17834702

申请日：2022-06-07

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Andrea Gotti

IPC: G11C13/00 ,  H10N70/00

Abstract: Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.

公开(公告)号：US12204597B2

公开(公告)日：2025-01-21

申请号：US18237702

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Carla L. Christensen ,  Venkata Kiran Kumar Matturi ,  Tara Gordon

IPC: G06F16/9535 ,  G06F16/9536 ,  G06F16/9538 ,  G06N3/063 ,  G06N3/08

Abstract: A processor of a host can define a plurality of relationships in a virtual environment. The processor of the host can also provide the plurality of inputs describing look preferences to an AI accelerator. The AI accelerator can receive the inputs. The AI accelerator can also generate a plurality of looks based on the plurality of relationships and the plurality of inputs.

公开(公告)号：US12202400B2

公开(公告)日：2025-01-21

申请号：US18326295

申请日：2023-05-31

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Robert Richard Noel Bielby

IPC: G08B21/24 ,  B60Q1/50 ,  B60Q5/00 ,  B60R11/04 ,  G06N3/08 ,  G06T7/73 ,  G06V10/764 ,  G06V10/82 ,  G06V20/59 ,  G08B21/22

Abstract: Systems, methods and apparatuses to detect an item left in a vehicle and to generate an alert about the item. For example, a camera configured in a vehicle can be used to monitor an item associated with a user of the vehicle. The item as in an image from the camera can be identified and recognized using an artificial neural network. In response to a determination that the item recognized in the image is left in the vehicle after the user has exited the vehicle, an alert is generated to indicate that an item is in the vehicle but the user is leaving the vehicle.

公开(公告)号：US20250022955A1

公开(公告)日：2025-01-16

申请号：US18904444

申请日：2024-10-02

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Hong Li ,  Erica L. Poelstra

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L23/49 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H10B12/00 ,  H10B63/00

Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.

公开(公告)号：US20250022852A1

公开(公告)日：2025-01-16

申请号：US18901972

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Chih Yuan Chang

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.

公开(公告)号：US20250022515A1

公开(公告)日：2025-01-16

申请号：US18767584

申请日：2024-07-09

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung LIEN ,  Dheeraj SRINIVASAN ,  Michael G. MILLER ,  Zhenming ZHOU

IPC: G11C16/10 ,  G11C16/34

Abstract: In some implementations, a memory device may receive, from a host device, a program command. The memory device may determine that the program command is associated with a single level cell (SLC) program command. The memory device may determine a size of host data associated with the program command. The memory device may select a programming scheme, from multiple candidate programming schemes, to be used to write the host data to a memory based on the size of the host data and based on determining that the program command is associated with the SLC program command. The memory device may write the host data to the memory using the programming scheme.

公开(公告)号：US20250022513A1

公开(公告)日：2025-01-16

申请号：US18903353

申请日：2024-10-01

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Yang ,  Ching-Huang Lu

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including identifying a plurality of wordlines at an initial voltage different from a pass-through voltage, and causing an early discharge sequence to be performed with respect to the plurality of wordlines. The early discharge sequence includes ramping at least a first set of wordlines of the plurality of wordlines from the initial voltage to a ramping voltage different from the pass-through voltage.