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公开(公告)号：US09461466B2
公开(公告)日：2016-10-04
申请号：US14229018
申请日：2014-03-28
Applicant: STMicroelectronics (Tours) SAS
Inventor： Jérôme Heurtier , Guillaume Bougrine , Arnaud Florence
IPC: H02H9/04
Abstract: An overvoltage protection device capable of protecting a power supply line and including in parallel a break-over diode, a controlled switch, and a circuit for controlling the switch.
Abstract translation: 一种过电压保护装置，其能够保护电源线并且并联包括断路二极管，受控开关和用于控制开关的电路。
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公开(公告)号：US09293939B2
公开(公告)日：2016-03-22
申请号：US14602015
申请日：2015-01-21
Applicant: STMicroelectronics (Tours) SAS
Inventor： Laurent Moindron , Sylvain Charley , Jérôme Heurtier
CPC classification number: H02J7/0072 , G01R27/2605 , H01Q5/335 , H02J7/0052 , H02J7/345 , H03J3/04
Abstract: A circuit for controlling a capacitor having a capacitance settable by biasing, including at least one terminal for receiving a digital set point value depending on the value desired for the capacitance, a circuit for determining a drift of the capacitance with respect to a nominal value, and a circuit of application of a correction to said digital set point value, depending on the determined drift.
Abstract translation: 一种用于控制电容器的电路，所述电容器具有通过偏置可设置的电容，所述电容器包括至少一个端子，用于接收取决于所述电容所需的值的数字设定值;电路，用于确定电容相对于标称值的漂移， 以及根据所确定的漂移对所述数字设定点值进行校正的电路。
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公开(公告)号：US20150108537A1
公开(公告)日：2015-04-23
申请号：US14510663
申请日：2014-10-09
Inventor： Samuel Menard , Gael Gautier
IPC: H01L29/747 , H01L29/66
CPC classification number: H01L29/66386 , H01L21/2885 , H01L21/76202 , H01L29/0615 , H01L29/0619 , H01L29/0642 , H01L29/0649 , H01L29/0661 , H01L29/32 , H01L29/456 , H01L29/747 , H01L29/87
Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well.
Abstract translation: 垂直功率部件包括在衬底的下表面上具有第二导电类型的阱的第一导电类型的硅衬底。 第一个阱在具有绝缘多孔硅环的部件周边上界定。 多孔硅环的上表面仅与第一导电类型的基板接触。 绝缘多孔硅环穿透衬底直至深度大于孔的厚度。
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公开(公告)号：US20140293493A1
公开(公告)日：2014-10-02
申请号：US14229018
申请日：2014-03-28
Applicant: STMicroelectronics (Tours) SAS
Inventor： Jérôme Heurtier , Guillaume Bougrine , Arnaud Florence
IPC: H02H9/04
Abstract: An overvoltage protection device capable of protecting a power supply line and including in parallel a break-over diode, a controlled switch, and a circuit for controlling the switch.
Abstract translation: 一种过电压保护装置，其能够保护电源线并且并联包括断路二极管，受控开关和用于控制开关的电路。
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公开(公告)号：US20140292614A1
公开(公告)日：2014-10-02
申请号：US14227532
申请日：2014-03-27
Applicant: STMicroelectronics (Tours) SAS
Inventor： Claire Laporte , Hilal Ezzeddine
IPC: H03H7/46
CPC classification number: H03H7/468 , H01P5/18 , H03F3/195 , H03F3/24 , H03F3/245 , H03F2200/171 , H03F2200/204 , H03F2200/207 , H03F2200/414 , H04B2001/0408
Abstract: A coupling circuit, including: a coupler including a first conductive line and a second conductive line coupled to the first one; at each end of the second line of the coupler, a two-output signal splitter; and at each output of each splitter, a filtering function.
Abstract translation: 一种耦合电路，包括：耦合器，包括耦合到第一导线的第一导线和耦合到第一导线的第二导线; 在耦合器的第二线的每一端处有两个输出信号分离器; 并且在每个分离器的每个输出处，具有滤波功能。
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Patent Agency Ranking
公开(公告)号：US08785297B2
公开(公告)日：2014-07-22
申请号：US13649797
申请日：2012-10-11
Applicant: STMicroelectronics (Tours) SAS
Inventor： Marc Feron , Vincent Jarry , Laurent Barreau
IPC: H01L21/30
CPC classification number: H01L25/0657 , H01L21/561 , H01L23/3114 , H01L25/50 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/01087
Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
Abstract translation: 一种封装电子部件的方法，包括以下步骤：在半导体晶片的第一表面中形成电子部件; 在第一表面上形成包括由绝缘材料分隔开的导电轨道和通孔的互连堆叠; 在互连堆叠上形成第一和第二接合焊盘; 至少在轮廓上除外，使晶片变薄; 用第一树脂层填充薄的区域; 在所述第一接合焊盘上布置至少一个第一芯片，并在所述第二焊盘上形成焊料凸块; 沉积覆盖第一芯片并部分覆盖焊料凸块的第二树脂层; 将粘合带粘合在第一树脂层上; 并将结构划分成单个芯片。
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257.发明授权公开(公告)号：US08772134B2
公开(公告)日：2014-07-08
申请号：US13783529
申请日：2013-03-04
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry , Patrick Hougron , Dominique Touzet , José Mendez
CPC classification number: H01L21/683 , H01L21/67132 , H01L21/78 , Y10T29/41 , Y10T83/02 , Y10T225/393
Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
Abstract translation: 一种用于从半导体晶片制造半导体芯片的方法，包括以下步骤：在第一支撑框架上紧固外部尺寸小于第一框架的外部尺寸并大于第一框架的内部尺寸的第二支撑框架 ; 将晶片布置在在第二框架上延伸的膜的表面上; 通过使用能够接收第一帧的设备进行晶片处理操作; 将第二框架与第一框架分离并移除第一框架; 并通过使用能够接收第二帧的设备进行晶片处理操作。
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公开(公告)号：US20140153759A1
公开(公告)日：2014-06-05
申请号：US14091824
申请日：2013-11-27
Applicant: STMicroelectronics (Tours) SAS
Inventor： Frédéric Cantin
IPC: H04R25/00
CPC classification number: H04R25/55 , H01M10/46 , H01M2220/30 , H04R2225/023 , H04R2225/31
Abstract: An object containing electronic circuits and a rechargeable cell, wherein the cell is arranged close to a surface of the object, a charge coil being shiftable with respect to the cell between an operating position where it is arranged around the cell and a recharge position where it is axially offset with respect to the cell.
Abstract translation: 一种包含电子电路和可充电电池的物体，其中所述电池靠近所述物体的表面布置，所述电荷线圈可相对于所述电池在围绕所述电池的布置的操作位置和所述电池的充电位置之间移动， 相对于电池轴向偏移。
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公开(公告)号：US20140043718A1
公开(公告)日：2014-02-13
申请号：US14056698
申请日：2013-10-17
Applicant: STMicroelectronics (Tours) SAS , STMicroelectronics S.r.l.
Inventor： Vincent Caro , Davide Rodilosso
IPC: H01G7/06
CPC classification number: H01G7/06 , H01L21/31111 , H01L28/55
Abstract: The disclosure concerns a method for etching a PVD deposited barium strontium titanate layer, wherein a non-ionic surfactant at a concentration between 0.1 and 1 percent is added to an acid etching solution.
Abstract translation: 本公开涉及一种用于蚀刻PVD沉积的钛酸钡锶钡层的方法，其中将0.1至1％浓度的非离子表面活性剂加入到酸蚀刻溶液中。
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公开(公告)号：US20140035132A1
公开(公告)日：2014-02-06
申请号：US13955325
申请日：2013-07-31
Inventor： Olivier Ory , Cedric Le Coq
IPC: H01L23/00
CPC classification number: H01L24/01 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/0603 , H01L2224/06051 , H01L2224/1403 , H01L2224/14051
Abstract: A surface mount chip including, on the side of a surface, first and second pads of connection to an external device, wherein, in top view, the first pad has an elongated general shape, and the second pad is a point-shaped pad which is not aligned with the first pad.
Abstract translation: 一种表面贴装芯片，其在表面侧包括与外部装置连接的第一和第二焊盘，其中，在顶视图中，第一焊盘具有细长的总体形状，第二焊盘是点状焊盘， 不与第一个垫对齐。
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