公开(公告)号：US06271563B1

公开(公告)日：2001-08-07

申请号：US09122815

申请日：1998-07-27

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L2976

CPC classification number: H01L29/66643 ,  H01L29/42376 ,  H01L29/4983

Abstract: A MOS transistor having a source and drain extension that are less than 40 nanometers in thickness to minimize the short channel effect. A gate includes a high-K dielectric spacer layer to create depletion regions in the substrate which form the drain and source extensions.

Abstract translation: 具有小于40纳米的源极和漏极延伸的MOS晶体管，以最小化短沟道效应。 栅极包括高K电介质间隔层，以在衬底中产生形成漏极和源极延伸的耗尽区。

公开(公告)号：US06268253B1

公开(公告)日：2001-07-31

申请号：US09418407

申请日：1999-10-14

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/28123 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

Abstract: A field effect transistor with scaled down dimensions is fabricated using a removable spacer having a substantially uniform width along the sidewalls of the gate of the field effect transistor during a differential RTA (Rapid Thermal Anneal) process. The removable spacer is formed on the sidewalls of the gate structure using the gate material on the sidewalls of the gate structure. Because the removable spacer has a width that is substantially uniform on the sidewalls of the gate of the MOSFET, the removable spacer may be readily etched using an dry etch process without adversely affecting other structures of the MOSFET. Exposed portions of the layer of gate dielectric are etched to form exposed portions of the active device area. A first dopant is then implanted into the exposed portions of the active device area to form a drain contact junction and a source contact junction of the field effect transistor. The first dopant is activated in the drain contact junction and the source contact junction using a first RTA (Rapid Thermal Anneal) process at a first temperature. The removable spacer is then etched from the sidewalls of the gate structure to form exposed extension implant areas in the active device area. A second dopant is then implanted into the exposed extension implant areas to form a drain extension implant and a source extension implant. The second dopant is then activated in the drain extension implant and the source extension implant using a second RTA (Rapid Thermal Anneal) process at a second temperature that is relatively lower than the first temperature of the first RTA process to preserve the shallow depth of the drain and source extension implants.

Abstract translation: 在差分RTA（快速热退火）过程期间，使用具有沿场效应晶体管的栅极的侧壁具有大致均匀宽度的可移除间隔物制造具有按比例缩小尺寸的场效应晶体管。 可移除间隔物使用栅极结构的侧壁上的栅极材料形成在栅极结构的侧壁上。 因为可移除的间隔物具有在MOSFET的栅极的侧壁上基本上均匀的宽度，所以可以使用干蚀刻工艺容易地蚀刻可去除间隔物，而不会对MOSFET的其它结构产生不利影响。 蚀刻栅极电介质层的暴露部分以形成有源器件区域的暴露部分。 然后将第一掺杂剂注入到有源器件区域的暴露部分中以形成漏极接触结和场效应晶体管的源极接触结。 第一掺杂剂在第一温度下使用第一RTA（快速热退火）工艺在漏极接触结和源极接触点处被激活。 然后从栅极结构的侧壁蚀刻可移除的间隔物，以在有源器件区域中形成暴露的延伸注入区域。 然后将第二掺杂剂注入到暴露的延伸植入区域中以形成漏极延伸植入物和源延伸植入物。 然后，第二掺杂剂在漏极延伸植入物和源延伸植入物中使用第二个RTA（快速热退火）工艺在比第一个RTA工艺的第一个温度低的第二个温度下被激活，以保持第二个RTA 排水和源延伸植入物。

公开(公告)号：US06200869B1

公开(公告)日：2001-03-13

申请号：US09187890

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用固相杂质源。 固相杂质源可以是约300nm厚的掺杂二氧化硅层。 该结构被热退火以将来自固相杂质源的掺杂剂驱动到源区和漏区。 来自杂质源的掺杂剂提供超浅源极和漏极延伸。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06194748B1

公开(公告)日：2001-02-27

申请号：US09303959

申请日：1999-05-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating an integrated circuit with less susceptibility to gate-edge fringing field effect is disclosed. The transistor includes a low-k dielectric spacer and a high-k gate dielectric. The high-k gate dielectric can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).

Abstract translation: 公开了一种制造具有对边缘边缘场效应较不敏感的集成电路的方法。 晶体管包括低k电介质隔离物和高k栅极电介质。 高k栅极电介质可以是五氧化钽或二氧化钛。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06180499B2

公开(公告)日：2001-01-30

申请号：US09162917

申请日：1998-09-29

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L29/4966 ,  H01L21/2807 ,  H01L21/32105 ,  H01L21/32155 ,  H01L21/823828

Abstract: A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a comparatively low dose, and then oxidizing the doped polysilicon layer. Under the influence of the oxidation, the germanium is repelled from an upper sacrificial region of the polysilicon layer into a lower gate region of the polysilicon layer, thereby increasing the germanium concentration in the lower gate region. The sacrificial region is then etched away and an undoped polysilicon film deposited on the gate region. Subsequently, the gate region with undoped polysilicon film is patterned to establish a MOSFET gate, with the substrate then being appropriately processed to establish MOSFET source/drain regions.

Abstract translation: 制造ULSI MOSFET芯片的方法包括在衬底上形成晶体管栅极。 栅极通过在衬底上沉积多晶硅层，以比较低的剂量将锗注入到多晶硅层中，然后氧化掺杂的多晶硅层而形成。 在氧化的影响下，锗从多晶硅层的上部牺牲区域排斥到多晶硅层的下部栅极区域，从而增加下部栅极区域中的锗浓度。 然后蚀刻掉牺牲区域，并且在栅极区域上沉积未掺杂的多晶硅膜。 随后，对具有未掺杂多晶硅膜的栅极区域进行构图以建立MOSFET栅极，然后适当地处理衬底以建立MOSFET源极/漏极区域。

公开(公告)号：US6114206A

公开(公告)日：2000-09-05

申请号：US187171

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/82345

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV. A damascene process can be utilized to fabricate the MOSFETs.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET包括具有多晶硅材料的栅极结构。 用较低浓度的锗注入多晶硅材料，其中需要较低的阈值电压MOSFET。 在锗的0-60％浓度范围内，阈值电压可以改变大约240mV。 可以使用镶嵌工艺来制造MOSFET。

公开(公告)号：US6100120A

公开(公告)日：2000-08-08

申请号：US309928

申请日：1999-05-11

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L22/00 ,  H01L21/84

CPC classification number: H01L21/28211 ,  H01L21/28229 ,  H01L29/517 ,  H01L29/66583

Abstract: A method of forming a dielectric gate insulator in a transistor is disclosed herein. The method includes depositing a layer of material over a semiconductor structure; depositing a covering layer over the layer of material; selectively creating an aperture in the covering layer, wherein an area of the layer of material is exposed; providing thermal oxidation to the exposed area of the layer of material to produce an oxidized area; providing a gate over the oxidized area; and removing the covering layer.

Abstract translation: 本文公开了在晶体管中形成电介质栅极绝缘体的方法。 该方法包括在半导体结构上沉积材料层; 在所述材料层上沉积覆盖层; 选择性地在所述覆盖层中产生孔，其中所述材料层的区域被暴露; 向所述材料层的暴露区域提供热氧化以产生氧化区域; 在氧化区域上设置一个门; 并去除覆盖层。

公开(公告)号：US6084271A

公开(公告)日：2000-07-04

申请号：US187892

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

公开(公告)号：US5985726A

公开(公告)日：1999-11-16

申请号：US187635

申请日：1998-11-06

Applicant: Bin Yu ,  Judy Xilin An

Inventor： Bin Yu ,  Judy Xilin An

IPC: H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66492 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dummy or sacrificial gate structure. Dopants are provided through the openings associated with sacrificial spacers to form the source and drain extensions. The openings can be filled with spacers The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用虚拟或牺牲栅极结构。 通过与牺牲间隔物相关联的开口提供掺杂剂以形成源极和漏极扩展。 开口可以填充间隔物该工艺可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US5880511A

公开(公告)日：1999-03-09

申请号：US497079

申请日：1995-06-30

Applicant: Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

Inventor： Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

IPC: H01L29/861 ,  H01L29/866

CPC classification number: H01L29/8618 ,  H01L29/861 ,  H01L29/866

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.0E17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 um. The thickness of the third (p+) region should be between about 0.3 um and about 2.0 um, and the thickness of the second (p-) region should be between about 0.5 um and about 5.0 um.

Abstract translation: 穿通二极管瞬态抑制器件具有改变掺杂浓度的基极区域，以改善泄漏和钳位特性。 穿通二极管包括包括n +区域的第一区域，包括邻接第一区域的p-区域的第二区域，包括邻接第二区域的p +区域的第三区域，以及包括邻接第三区域的n +区域的第四区域 地区。 n +层的峰值掺杂剂浓度应为约1.5E18cm-3，p +层的峰值掺杂剂浓度应在n +层的峰值浓度的约1至约5倍之间， 层应在约0.5E14cm-3和约1.0E17cm-3之间。 第四（n +）区域的结深度应大于约0.3μm。 第三（p +）区域的厚度应在约0.3μm至约2.0μm之间，第二（p-）区域的厚度应在约0.5μm至约5.0μm之间。