公开(公告)号：US20190393335A1

公开(公告)日：2019-12-26

申请号：US16016828

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

公开(公告)号：US20190393321A1

公开(公告)日：2019-12-26

申请号：US16014076

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Scott Beasor

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Various processes form different structures including exemplary apparatuses that include (among other components) a first layer having channel regions, source/drain structures in the first layer on opposite sides of the channel regions, a gate insulator on the channel region, and a gate stack on the gate insulator. The gate stack can include a gate conductor, and a stack insulator or a gate contact on the gate conductor. The gate stack has lower sidewalls adjacent to the source/drain structures and upper sidewalls distal to the source/drain structures. Further, lower spacers are between the source/drain contacts and the lower sidewalls of the gate stack; and upper spacers between the source/drain contacts and the upper sidewalls of the gate stack. In some structures, the upper spacers can partially overlap the lower spacers.

公开(公告)号：US10510749B1

公开(公告)日：2019-12-17

申请号：US16057881

申请日：2018-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos ,  Garo J. Derderian

IPC: H01L29/76 ,  H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06

Abstract: A resistor for an integrated circuit (IC), an IC and a related method are disclosed. The resistor may include a metal alloy resistor body positioned within a single diffusion break (SDB). The SDB provides an isolation region in a semiconductor fin between a pair of fin-type field effect transistors (finFETs). The resistor in the SDB allows for the resistor to be built at front-end-of-line (FEOL) layers, which saves on space and expense, and allows for precise dimensions for the resistor.

公开(公告)号：US20190355615A1

公开(公告)日：2019-11-21

申请号：US16525601

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

公开(公告)号：US10483377B2

公开(公告)日：2019-11-19

申请号：US15821091

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L29/66 ,  H01L29/78

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

公开(公告)号：US10475899B2

公开(公告)日：2019-11-12

申请号：US16190549

申请日：2018-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L27/088

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US10461173B1

公开(公告)日：2019-10-29

申请号：US15990186

申请日：2018-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Xuan Anh Tran ,  Hui Zang ,  Bala Haran ,  Suryanarayana Kalaga

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.

公开(公告)号：US20190319112A1

公开(公告)日：2019-10-17

申请号：US15951621

申请日：2018-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/02

Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.

公开(公告)号：US20190318931A1

公开(公告)日：2019-10-17

申请号：US15950364

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaohan Wang ,  Qiang Fang ,  Zhiguo Sun ,  Jinping Liu ,  Hui Zang

IPC: H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

公开(公告)号：US10446654B1

公开(公告)日：2019-10-15

申请号：US16008711

申请日：2018-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L29/76 ,  H01L29/417 ,  H01L21/768 ,  H01L29/51 ,  H01L29/45

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate contact structures and self-aligned contact process and methods of manufacture. The structure includes: a gate structure having source and drain regions; a first metal contacting the source and drain regions; a second metal over the first metal in the source and drain regions; and a capping material over the first metal and over the gate structure.