公开(公告)号：US20140252543A1

公开(公告)日：2014-09-11

申请号：US13784895

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/88 ,  H01L28/92 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure.

Abstract translation: 特定的金属氧化物金属（MOM）电容器器件包括耦合到衬底的导电栅极材料。 MOM电容器装置还包括耦合到导电栅极材料的第一金属结构。 MOM电容器装置还包括耦合到衬底并且靠近第一金属结构的第二金属结构。

公开(公告)号：US08796046B2

公开(公告)日：2014-08-05

申请号：US14036354

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L29/82 ,  G11C11/16 ,  H01L27/22 ,  H01L27/115 ,  H01L43/08

CPC classification number: G11C11/16 ,  G11C11/161 ,  H01L23/552 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via.

Abstract translation: 提供了用于屏蔽屏蔽非易失性存储器的方法和装置，例如屏蔽磁性隧道结（MTJ）装置与磁通量。 在一个示例中，屏蔽层邻近MTJ器件的电极形成，使得屏蔽层基本上围绕电极的表面，并且金属线耦合到屏蔽层。 金属线可以通过通孔耦合到屏蔽层。

公开(公告)号：US20140043924A1

公开(公告)日：2014-02-13

申请号：US14056990

申请日：2013-10-18

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Hari M. Rao ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L43/12

CPC classification number: G11C11/1677 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/161 ,  G11C29/18 ,  G11C29/30 ,  G11C2029/1202 ,  G11C2029/2602 ,  H01L43/12

Abstract: Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.

Abstract translation: 所公开的实施例包括具有多个位线和多个排列成列的源极线的存储器阵列。 多行字线被排列成行。 多个存储元件具有与存储器阵列电分离的存储元件的第一子集和耦合到存储器阵列的存储元件的第二子集。 存储器阵列还包括多个位单元，每个位单元包括来自耦合到至少两个晶体管的存储元件的第二子集的一个存储元件。 位单元耦合到多个位线和多个源极线。 每个晶体管耦合到一个字线。 存储器阵列还可以包括选择高性能模式和高密度模式的逻辑。

公开(公告)号：US20140015080A1

公开(公告)日：2014-01-16

申请号：US14036409

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Seung H. Kang ,  Xia Li ,  Shiqun Gu ,  Kangho Lee ,  Xiaochun Zhu

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device.

Abstract translation: 用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）装置包括与至少一个控制装置通信的第一导电互连和通过形成在电介质钝化屏障中的通孔连接到第一导电互连的第一电极，其使用 第一个面具。 该装置具有用于存储耦合到第一电极的数据的MTJ堆叠。 MTJ堆叠的一部分具有基于第二掩模的横向尺寸。 由第二掩模限定的部分在接触通孔之上。 第二电极耦合到MTJ堆叠并且还具有由第二掩模限定的横向尺寸。 第一电极和MTJ堆叠的一部分由第三掩模限定。 第二导电互连件耦合到第二电极和至少一个其它控制装置。

公开(公告)号：US20140001568A1

公开(公告)日：2014-01-02

申请号：US13684107

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Zhongze Wang ,  John J. Zhu ,  Xia Li

IPC: H01L27/112 ,  H01L21/8239

CPC classification number: H01L27/11206 ,  G11C17/16 ,  G11C17/165 ,  H01L21/8239 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/1052 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.

Abstract translation: 一个特征涉及一种集成电路，包括存取晶体管和反熔丝。 存取晶体管包括至少一个源极/漏极区域，反熔丝具有导体 - 绝缘体 - 导体结构。 反熔丝包括用作第一电极的第一导体，并且还包括反熔丝电介质和第二导体。 第一电极的第一表面耦合到反熔丝电介质的第一表面，反熔丝电介质的第二表面耦合到第二导体的第一表面。 第二导体电耦合到存取晶体管的源/漏区。 如果在第一电极和第二导体之间施加大于或等于抗熔丝电介质击穿电压的编程电压Vpp，则反熔丝适于从开路状态转换到闭合电路状态。

公开(公告)号：US20130320468A1

公开(公告)日：2013-12-05

申请号：US13959710

申请日：2013-08-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/10 ,  H01L43/12

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/12

Abstract: According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

Abstract translation: 根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。 存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。 绝缘层设置在参考和存储铁磁层之间。

公开(公告)号：US20130235639A1

公开(公告)日：2013-09-12

申请号：US13869086

申请日：2013-04-24

Applicant: QUALCOMM INCORPORATED

Inventor： Kangho Lee ,  Taehyun Kim ,  Xia Li ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C5/02 ,  G11C5/08

CPC classification number: G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

Abstract: A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

Abstract translation: 大型存储器阵列包括a。 均匀大小的虚拟位单元和有源位单元的统一模式。 大规模存储器阵列中的子阵列由虚拟位单元分隔开。 信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。 类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。

公开(公告)号：US20130153854A1

公开(公告)日：2013-06-20

申请号：US13762424

申请日：2013-02-08

Applicant: Qualcomm Incorporated

Inventor： Xia Li

IPC: H01L45/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/52 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

Abstract: A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.

Abstract translation: 公开了形成相变随机存取存储器（PRAM）单元的方法以及相变随机存取存储器（PRAM）单元的结构。 PRAM单元包括底电极，耦合到底电极的加热电阻器，形成在加热电阻器上并耦合到加热电阻器的相变材料（PCM）以及耦合到相变材料的顶电极。 相变材料接触加热器电阻器的垂直表面的一部分和加热电阻器的水平表面的一部分，以在加热电阻器和相变材料之间形成有源区域。