公开(公告)号：US10348332B2

公开(公告)日：2019-07-09

申请号：US16132461

申请日：2018-09-16

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/11 ,  G06F11/14 ,  G06F12/02 ,  G06F12/0802 ,  G11C7/10 ,  G11C11/56 ,  G11C16/04 ,  G11C29/52 ,  G11C16/08

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

公开(公告)号：US10324789B2

公开(公告)日：2019-06-18

申请号：US16115570

申请日：2018-08-29

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/56 ,  G11C29/52 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: A method for accessing a flash memory module includes: sequentially writing Nth−(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth−(N+K)th data to generate Nth−(N+K)th ECCs, respectively, where the Nth−(N+K)th ECCs are used to correct errors of the Nth−(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth−(N+K)th ECCs to generate the (N+K+1)th ECC.

公开(公告)号：US10235075B2

公开(公告)日：2019-03-19

申请号：US15985718

申请日：2018-05-22

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C11/34 ,  G11C16/04 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode.

公开(公告)号：US20190074067A1

公开(公告)日：2019-03-07

申请号：US16178612

申请日：2018-11-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G06F3/06 ,  H03M13/15 ,  G11C29/52 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  G11C2211/5644 ,  G11C2211/5648 ,  H03M13/152

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

公开(公告)号：US20190050287A1

公开(公告)日：2019-02-14

申请号：US16057839

申请日：2018-08-08

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/45

Abstract: The present invention provides a decoding method of a flash memory controller, wherein the decoding method includes the steps of: reading first data from a flash memory module; decoding the first data, and recording at least one specific address of the flash memory module according to decoding results of the first data, wherein said at least one specific address corresponds to a bit having high reliability errors (HRE) of the first data; reading second data from the flash memory module; and decoding the second data according to said at least one specific address.

公开(公告)号：US20180210788A1

公开(公告)日：2018-07-26

申请号：US15927069

申请日：2018-03-20

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  H03M13/11 ,  G11C11/56 ,  G11C29/52 ,  G11C16/26

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

公开(公告)号：US10025662B2

公开(公告)日：2018-07-17

申请号：US15876211

申请日：2018-01-22

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu ,  Jian-Dong Du

IPC: G11C16/04 ,  G06F11/10 ,  G11C29/52 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418 ,  G11C29/52

Abstract: A method used in a flash memory module having a plurality of storage blocks is disclosed. Each storage block can be used as a first block or a second block wherein a cell of the first block is arranged for storing data of 1 bit and a cell of the second block is arranged for storing data of at least 2 bits. The method includes: classifying data to be programmed into a plurality of groups of data; executing error code encoding to generate a corresponding parity check code to store the groups of data and the corresponding parity check code to at least one block of first blocks; and after completing storing the groups of data, performing an internal copy operation upon the groups of data and the corresponding parity check code from the at least one block of the first blocks to at least one second block.

公开(公告)号：US10007460B2

公开(公告)日：2018-06-26

申请号：US15643501

申请日：2017-07-07

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C11/34 ,  G11C16/04 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US09910772B2

公开(公告)日：2018-03-06

申请号：US15497185

申请日：2017-04-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G11C16/04 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0629 ,  G06F11/1004 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C2211/5641

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

公开(公告)号：US20180018224A1

公开(公告)日：2018-01-18

申请号：US15717970

申请日：2017-09-28

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Li-Sheng Kan

IPC: G06F11/10 ,  G06F3/00 ,  G06F11/14 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F3/00 ,  G06F11/14 ,  G06F12/0246 ,  G06F2212/1032

Abstract: A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result.