Epitaxial semiconductor material regions for transistor devices and methods of forming same

    公开(公告)号:US11205699B2

    公开(公告)日:2021-12-21

    申请号:US16655429

    申请日:2019-10-17

    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.

    TRANSISTORS WITH SECTIONED EXTENSION REGIONS

    公开(公告)号:US20210391425A1

    公开(公告)日:2021-12-16

    申请号:US16899086

    申请日:2020-06-11

    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is formed over a channel region of a substrate. A first source/drain region is positioned in the substrate adjacent to a first sidewall of the gate structure, a second source/drain region is positioned in the substrate adjacent to a second sidewall of the gate structure, and an extension region is positioned in the substrate. The extension region includes first and second sections that each overlap with the first source/drain region. The first and second sections of the extension region are spaced apart along a longitudinal axis of the gate structure. A portion of the channel region is positioned along the longitudinal axis of the gate structure between the first and second sections of the extension region.

    PHOTODIODE AND/OR PIN DIODE STRUCTURES

    公开(公告)号:US20210376180A1

    公开(公告)日:2021-12-02

    申请号:US16887375

    申请日:2020-05-29

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.

    CORNER STRUCTURES FOR AN OPTICAL FIBER GROOVE

    公开(公告)号:US20210375788A1

    公开(公告)日:2021-12-02

    申请号:US17400847

    申请日:2021-08-12

    Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

    Polarization-insensitive directional couplers

    公开(公告)号:US11181693B1

    公开(公告)日:2021-11-23

    申请号:US17076326

    申请日:2020-10-21

    Inventor: Yusheng Bian

    Abstract: Structures for a directional coupler and methods of fabricating a structure for a directional coupler. A first waveguide core has a first section, a second waveguide core has a second section laterally adjacent to the first section, a third waveguide core has a first taper, a second taper, and a third section longitudinally positioned between the first taper and the second taper, and a fourth waveguide core has a first taper, a second taper, and a fourth section longitudinally positioned between the first taper and the second taper. The fourth section is laterally adjacent to the third section, and the third section and the fourth section are positioned either over or under the first section and the second section.

    WAFER-LEVEL TESTING OF LASERS ATTACHED TO PHOTONICS CHIPS

    公开(公告)号:US20210356684A1

    公开(公告)日:2021-11-18

    申请号:US15930876

    申请日:2020-05-13

    Inventor: Zhuojie Wu Bo Peng

    Abstract: Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.

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