公开(公告)号：US08369401B1

公开(公告)日：2013-02-05

申请号：US10333433

申请日：2000-10-06

Applicant: Kwong Huang Goh ,  Lucas Y. W. Hui

Inventor： Kwong Huang Goh ,  Lucas Y. W. Hui

IPC: H04N11/02

CPC classification number: H04N5/147 ,  H04N19/115 ,  H04N19/14 ,  H04N19/142 ,  H04N19/149 ,  H04N19/159 ,  H04N19/172 ,  H04N19/177 ,  H04N19/179 ,  H04N19/61 ,  H04N19/87

Abstract: The invention relates to a method of bit allocation in a scene change situation during encoding a video sequence. Following a scene change, the picture complexity of the current picture is adjusted so that the bit allocation for the next picture is more accurately estimated.

Abstract translation: 本发明涉及一种在编码视频序列期间场景变化情况下的比特分配方法。 在场景变化之后，调整当前图像的图像复杂度，使得下一图像的比特分配被更准确地估计。

公开(公告)号：US08338943B2

公开(公告)日：2012-12-25

申请号：US12873068

申请日：2010-08-31

Applicant: Kum Weng Loo

Inventor： Kum Weng Loo

IPC: H01L23/10 ,  H01L23/34

CPC classification number: H01L23/367 ,  H01L21/50 ,  H01L23/16 ,  H01L23/42 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83 ,  H01L2924/0001 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, a stiffener ring coupled to the substrate and configured to form a well with the substrate, and a die positioned in the well. A thermal interface is positioned on the die. A heat spreader is coupled to the stiffener ring so that a portion of the heat spreader is positioned in the well and the thermal interface thermally couples the heat spreader to the die. The portion of the heat spreader positioned in the well adds rigidity to the semiconductor package and facilitates the use of thin dies.

Abstract translation: 半导体封装包括衬底，耦合到衬底并且被配置为与衬底形成阱的加强环和定位在阱中的管芯。 热界面位于模具上。 散热器耦合到加强环，使得散热器的一部分定位在井中，并且热界面将散热器热耦合到管芯。 定位在井中的散热器部分增加了半导体封装的刚性，并且便于使用薄模。

公开(公告)号：US08332229B2

公开(公告)日：2012-12-11

申请号：US12405133

申请日：2009-03-16

Applicant: Samsudin ,  Sapna George

Inventor： Samsudin ,  Sapna George

IPC: G10L19/00 ,  H04R5/027

CPC classification number: G10L19/0208 ,  G10L19/008

Abstract: The invention provides for the encoding of surround sound produced by any coincident microphone techniques with coincident-to-virtual microphone signal matrixing. An encoding scheme provides significantly lower computational demand, by deriving the spatial parameters and output downmixes from the coincident microphone array signals and the coincident-to-surround channel-coefficients matrix, instead of the multi-channel signals.

Abstract translation: 本发明提供了通过符合虚拟麦克风信号矩阵的任何重合麦克风技术产生的环绕声的编码。 编码方案通过从重合的麦克风阵列信号和重合环绕声道系数矩阵中导出空间参数和输出下混而提供显着更低的计算需求，而不是多声道信号。

公开(公告)号：US08299817B2

公开(公告)日：2012-10-30

申请号：US12957046

申请日：2010-11-30

Applicant: Beng-Heng Goh ,  Srijith Varma Vijaya Varma

Inventor： Beng-Heng Goh ,  Srijith Varma Vijaya Varma

IPC: G09G5/02 ,  H03K19/173

CPC classification number: G09G3/2044 ,  G09G2310/0286 ,  G09G2320/0223

Abstract: Vertical dithering is performed for vertical droop compensation in image processing using Linear Feedback Shift Registers (LFSRs). Line memories are not used. A compensation circuit includes a signature reload input signal coupled to the input of five LFSRs. Each LFSR includes a signature store. The output of each LFSR provides a sequence output signal that is gated with a corresponding enable signal in a first logic circuit. The output of all of the first logic circuits are combined in a second logic circuit to provide a control signal output.

Abstract translation: 在使用线性反馈移位寄存器（LFSR）的图像处理中，执行垂直垂直垂直抖动。 行记忆不被使用。 补偿电路包括耦合到五个LFSR的输入的签名重新加载输入信号。 每个LFSR都包括一个签名商店。 每个LFSR的输出提供在第一逻辑电路中与相应使能信号选通的序列输出信号。 所有第一逻辑电路的输出在第二逻辑电路中组合以提供控制信号输出。

公开(公告)号：US08292185B2

公开(公告)日：2012-10-23

申请号：US11259974

申请日：2005-10-26

Applicant: Kian-Ann Ng

Inventor： Kian-Ann Ng

IPC: G06K13/00

CPC classification number: G06K19/0723 ,  G06K19/0701

Abstract: A circuit includes an antenna terminal for generating a current through electromagnetic induction. The circuit also includes a rectifier for receiving the current and generating a rectified power supply voltage. In addition, the circuit includes a voltage clamp for sinking at least some of the current from the antenna terminal based on the rectified power supply voltage from the rectifier. The voltage clamp could include a control circuit (such as an N-channel transistor and a resistor) for controlling the sinking of at least some of the current from the antenna terminal. The voltage clamp could also include a sink circuit (such as an N-channel transistor) for sinking at least some of the current from the antenna terminal. The voltage clamp could further include a sink control circuit (such as a P-channel transistor and a resistor) for activating and deactivating the sink circuit based on operation of the control circuit.

Abstract translation: 电路包括用于通过电磁感应产生电流的天线端子。 电路还包括用于接收电流并产生整流电源电压的整流器。 此外，该电路包括用于从整流器基于经整流的电源电压从天线端子吸收至少一些电流的电压钳。 电压钳可以包括用于控制来自天线端子的至少一些电流的吸收的控制电路（例如N沟道晶体管和电阻器）。 电压钳还可以包括用于从天线端子吸收至少一些电流的汇流电路（例如N沟道晶体管）。 电压钳还可以包括用于基于控制电路的操作激活和去激活吸收电路的吸收器控制电路（例如P沟道晶体管和电阻器）。

公开(公告)号：US08278146B2

公开(公告)日：2012-10-02

申请号：US12330143

申请日：2008-12-08

Applicant: Jing-en Luan

Inventor： Jing-en Luan

IPC: H01L21/00 ,  H01L23/28 ,  H01L23/48 ,  H01L23/482 ,  H01L25/16

CPC classification number: H01L23/3128 ,  H01L24/28 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.

Abstract translation: 芯片封装包括基板，靠近基板的顶表面的集成电路，以及包括将集成电路封装在基板的顶表面的至少一部分上的密封剂的盖。 芯片封装进一步包括位于衬底的顶表面的至少一部分上的至少一个延伸特征。 所述至少一个延伸部件还包括所述密封剂并且从所述盖延伸到所述基板的周边。

公开(公告)号：US20120235254A1

公开(公告)日：2012-09-20

申请号：US13485434

申请日：2012-05-31

Applicant: Venkatesh Mohanakrishnaswamy ,  Olivier Le Neel ,  Loi N. Nguyen

Inventor： Venkatesh Mohanakrishnaswamy ,  Olivier Le Neel ,  Loi N. Nguyen

IPC: H01L27/20 ,  H01L21/77

CPC classification number: H01L27/0617 ,  B81C1/00246 ,  B81C2203/0742 ,  H01L27/0611

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract translation: 提出了一种方法，其包括形成具有第一掺杂剂浓度的第一层，所述第一层具有集成电路区域和微机电区域，并且掺杂第一层的微机电区域以具有第二掺杂剂浓度。 该方法包括形成具有覆盖在第一层上的第三掺杂剂浓度的第二层，掺杂覆盖在微机电区域上的第二层以具有第四掺杂剂浓度，在微机电区域中使用第一层 和第二层，并且使用第二层在集成电路区域中形成有源部件。

公开(公告)号：US08217518B2

公开(公告)日：2012-07-10

申请号：US11715261

申请日：2007-03-07

Applicant: Tong Yan Tee ,  Xueren Zhang ,  Shanzhong Wang ,  Valeriy Nosik ,  Jijie Zhou ,  Sridhar Idapalapati ,  Subodh Mhaisalkar ,  Zhi Yuan Shane Loo

Inventor： Tong Yan Tee ,  Xueren Zhang ,  Shanzhong Wang ,  Valeriy Nosik ,  Jijie Zhou ,  Sridhar Idapalapati ,  Subodh Mhaisalkar ,  Zhi Yuan Shane Loo

IPC: H01L23/373

CPC classification number: H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/785 ,  H01L2924/00

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract translation: 在互连结构上涂覆或以其它方式形成保护层。 互连结构包括金属线（例如通过金属通孔连接的顶部和底部金属层）和低K材料。 保护层包括垂直排列的电介质或分散有碳纳米管的其它材料。 保护层可以包括一层或多层碳纳米管，并且碳纳米管可以在保护层的每个层中具有任何合适的分散体，取向和图案。 除其他之外，碳纳米管有助于减少或防止互连结构的损坏，例如通过减少或防止低K材料的塌陷或金属线与低K材料之间的分层。

公开(公告)号：US20120170864A1

公开(公告)日：2012-07-05

申请号：US13332949

申请日：2011-12-21

Applicant: Anna Raffalli ,  Haiyun Wang ,  Lucas Hui ,  Patricia Chiang

Inventor： Anna Raffalli ,  Haiyun Wang ,  Lucas Hui ,  Patricia Chiang

IPC: G06K9/40

CPC classification number: H04N19/00066 ,  H04N19/117 ,  H04N19/14 ,  H04N19/86

Abstract: Systems and methods are disclosed for determining the perceptibility of noise in a block of images and/or video. The systems and methods may compute a mask value for the block using a block masking generator. The mask value may indicate the perceptibility of noise in the block. The mask value may be computed using a normalized activity value and/or a texture value for the block. The normalized activity value may indicate the relative activity in the block as compared to the activity in the image and/or video. The texture value may indicate the strength and/or number of edges in the block.

Abstract translation: 公开了用于确定图像和/或视频块中的噪声的感知性的系统和方法。 系统和方法可以使用块掩码生成器来计算块的掩码值。 掩模值可以指示块中的噪声的可感知性。 可以使用归一化活动值和/或块的纹理值来计算掩模值。 与图像和/或视频中的活动相比，归一化活动值可以指示块中的相对活动。 纹理值可以指示块中的边缘的强度和/或数量。

公开(公告)号：US20120168909A1

公开(公告)日：2012-07-05

申请号：US13334087

申请日：2011-12-22

Applicant: Alfonso Patti ,  Antonino Schillaci ,  Bartolome Marrone ,  Gianleonardo Grasso ,  Rajesh Kumar

Inventor： Alfonso Patti ,  Antonino Schillaci ,  Bartolome Marrone ,  Gianleonardo Grasso ,  Rajesh Kumar

IPC: H01L21/331 ,  H01L29/73

CPC classification number: H01L29/402 ,  H01L29/66272 ,  H01L29/7322

Abstract: A method for integrating a bipolar injunction transistor in a semiconductor chip includes the steps of forming an intrinsic base region of a second type of conductivity extending in the collector region from a main surface through an intrinsic base window of the sacrificial insulating layer, forming an emitter region of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window of the sacrificial insulating layer, removing the sacrificial insulating layer, forming an intermediate insulating layer on the main surface, and forming an extrinsic base region of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window of the intermediate insulating layer

Abstract translation: 一种用于在半导体芯片中积分双极性抑制晶体管的方法包括以下步骤：在主表面通过牺牲绝缘层的本征基极窗形成在集电极区域中延伸的第二类型导电的本征基极区域，形成发射极 所述第一类型的导电性区域从所述主表面延伸穿过所述牺牲绝缘层的发射极窗口，去除所述牺牲绝缘层，在所述主表面上形成中间绝缘层，以及形成所述牺牲绝缘层的外部基极区域 该第二类型的导电性在本征基区中从主表面穿过中间绝缘层的非本征基窗延伸