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    Enhancing metal/low-K interconnect reliability using a protection layer
    4.
    发明申请
    Enhancing metal/low-K interconnect reliability using a protection layer 有权
    使用保护层增强金属/低K互连可靠性

    公开(公告)号：US20070216032A1

    公开(公告)日：2007-09-20

    申请号：US11715261

    申请日：2007-03-07

    申请人： Tong Tee ,  Xueren Zhang ,  Shanzhong Wang ,  Valeriy Nosik ,  Jijie Zhou ,  Sridhar Idapalapati ,  Subodh Mhaisalkar ,  Zhi Yuan Loo

    发明人： Tong Tee ,  Xueren Zhang ,  Shanzhong Wang ,  Valeriy Nosik ,  Jijie Zhou ,  Sridhar Idapalapati ,  Subodh Mhaisalkar ,  Zhi Yuan Loo

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/785 ,  H01L2924/00

    摘要： A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

    摘要翻译： 在互连结构上涂覆或以其它方式形成保护层。 互连结构包括金属线（例如通过金属通孔连接的顶部和底部金属层）和低K材料。 保护层包括垂直排列的电介质或分散有碳纳米管的其它材料。 保护层可以包括一层或多层碳纳米管，并且碳纳米管可以在保护层的每个层中具有任何合适的分散体，取向和图案。 除其他之外，碳纳米管有助于减少或防止互连结构的损坏，例如通过减少或防止低K材料的塌陷或金属线与低K材料之间的分层。

    Carbon nanotube-modified low-K materials
    5.
    发明授权
    Carbon nanotube-modified low-K materials 有权
    碳纳米管改性低K材料

    公开(公告)号：US08592980B2

    公开(公告)日：2013-11-26

    申请号：US11715260

    申请日：2007-03-07

    申请人： Shanzhong Wang ,  Valeriy Nosik ,  Tong Yan Tee ,  Xueren Zhang

    发明人： Shanzhong Wang ,  Valeriy Nosik ,  Tong Yan Tee ,  Xueren Zhang

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

    CPC分类号： H01L23/5329 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.

    摘要翻译： 提供了一种用于集成电路的互连结构。 互连结构包括第一低K电介质材料。 第一低K材料可以用第一组碳纳米管（CNT）进行改性并设置在金属线上。 通过将第一组CNT分散在溶液中来将第一低K材料进行改性，将溶液旋转到硅晶片上并固化该溶液以形成用第一CNT改性的第一低K材料。 金属线包括由金属通孔连接的顶层和底层。 互连结构还包括用第二组CNT修饰并设置在底层上的第二低K电介质材料。 因此，本公开的实施例可以有助于增加低K材料或整个互连结构的机械强度。

    Carbon nanotube-modified low-K materials
    6.
    发明申请
    Carbon nanotube-modified low-K materials 有权
    碳纳米管改性低K材料

    公开(公告)号：US20070210455A1

    公开(公告)日：2007-09-13

    申请号：US11715260

    申请日：2007-03-07

    申请人： Shanzhong Wang ,  Valeriy Nosik ,  Tong Tee ,  Xueren Zhang

    发明人： Shanzhong Wang ,  Valeriy Nosik ,  Tong Tee ,  Xueren Zhang

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5329 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.

    摘要翻译： 提供了一种用于集成电路的互连结构。 互连结构包括第一低K电介质材料。 第一低K材料可以用第一组碳纳米管（CNT）进行改性并设置在金属线上。 通过将第一组CNT分散在溶液中来将第一低K材料进行改性，将溶液旋转到硅晶片上并固化该溶液以形成用第一CNT改性的第一低K材料。 金属线包括由金属通孔连接的顶层和底层。 互连结构还包括用第二组CNT修饰并设置在底层上的第二低K电介质材料。 因此，本公开的实施例可以有助于增加低K材料或整个互连结构的机械强度。

    Piezo-resistive force sensor with bumps on membrane structure
    7.
    发明授权
    Piezo-resistive force sensor with bumps on membrane structure 有权
    具有膜结构凸起的压电阻力传感器

    公开(公告)号：US08800391B2

    公开(公告)日：2014-08-12

    申请号：US11803152

    申请日：2007-05-11

    申请人： Xueren Zhang ,  Andrea Lorenzo Vitali ,  Federico Giovanni Ziglioli ,  Bruno Biffi ,  Tong Yan Tee

    发明人： Xueren Zhang ,  Andrea Lorenzo Vitali ,  Federico Giovanni Ziglioli ,  Bruno Biffi ,  Tong Yan Tee

    IPC分类号： G01L1/04 ,  G01L1/18

    CPC分类号： G01L1/2231 ,  G01L1/18

    摘要： A force sensor to measure a force from a load includes a plunger, a flexible disc-shaped membrane, a support plate and a silicon die. The plunger is configured to receive the force from the load, and has a ring-shaped groove at the lower surface. The membrane has a ring-shaped upper bump at the upper surface configured to complementarily fit into the groove at the lower surface of plunger and a ring-shaped lower bump at lower upper surface. The support plate has a ring-shaped groove for complementary fit into the lower bump on the lower surface of the membrane. The silicon die is centrally mounted on the membrane and comprises piezo-resistors with resistance that varies when deformed by the force. Force received by the plunger is transmitted to the membrane, causing the membrane to flex and bending or compressing of the silicon die, resulting in the measurement of the force.

    摘要翻译： 用于测量来自负载的力的力传感器包括柱塞，柔性盘形膜，支撑板和硅模头。 柱塞被构造成接收来自负载的力，并且在下表面具有环形槽。 膜在上表面具有环形上凸起，构造成互补配合在柱塞下表面的凹槽中，下表面具有环形下凸块。 支撑板具有用于互补配合到膜下表面上的下凸块的环形槽。 硅片中心地安装在膜上，并且包括压电电阻器，其具有随着力的变形而变化的电阻。 由柱塞接收的力传递到膜，导致膜弯曲或压缩硅模，从而测量力。

    Piezo-resistive force sensor with bumps on membrane structure
    8.
    发明申请
    Piezo-resistive force sensor with bumps on membrane structure 有权
    具有膜结构凸起的压电阻力传感器

    公开(公告)号：US20080178691A1

    公开(公告)日：2008-07-31

    申请号：US11803152

    申请日：2007-05-11

    申请人： Xueren Zhang ,  Andrea Lorenzo Vitali ,  Federico Giovanni Ziglioli ,  Bruno Biffi ,  Tong Yan Tee

    发明人： Xueren Zhang ,  Andrea Lorenzo Vitali ,  Federico Giovanni Ziglioli ,  Bruno Biffi ,  Tong Yan Tee

    IPC分类号： G01L1/16

    CPC分类号： G01L1/2231 ,  G01L1/18

    摘要： A force sensor to measure a force from a load. The force sensor includes a plunger, a flexible disc-shaped membrane, a support plate and a silicon die. The plunger is configured to receive the force from the load, and has a ring-shaped groove at the lower surface. The membrane has a ring-shaped upper bump at the upper surface, wherein the upper bump is configured to complementarily fit into the groove at the lower surface of plunger. Furthermore, the membrane has a ring-shaped lower bump at lower upper surface. The support plate has a ring-shaped groove that is configured so that the lower bump on the lower surface of the membrane can complementarily fit into. The silicon die is centrally mounted on the membrane, where the silicon die comprises piezo-resistors that vary their resistance when deformed by the force. In particular, the force received by the plunger from the load is transmitted to the membrane, causing the membrane to flex, which in turn causes the bending or compressing of the silicon die, resulting in the measurement of the force from the load.

    摘要翻译： 用于测量来自负载的力的力传感器。 力传感器包括柱塞，柔性盘形膜，支撑板和硅模头。 柱塞被构造成接收来自负载的力，并且在下表面具有环形槽。 膜在上表面具有环形上凸起，其中上凸起构造成互补配合在柱塞下表面的凹槽中。 此外，膜在较低的上表面具有环形的下凸起。 支撑板具有环形槽，其被构造成使得膜的下表面上的下凸块可以互补地配合。 硅芯片集中安装在膜上，其中硅片包括压电阻器，其在通过力变形时改变其电阻。 特别地，柱塞从负载接收的力传递到膜，导致膜弯曲，这又导致硅模的弯曲或压缩，导致测量来自负载的力。

    Window clamp top plate for integrated circuit packaging
    9.
    发明授权
    Window clamp top plate for integrated circuit packaging 有权
    窗夹板顶板用于集成电路封装

    公开(公告)号：US08796826B2

    公开(公告)日：2014-08-05

    申请号：US13335467

    申请日：2011-12-22

    申请人： Xueren Zhang ,  Kim-Yong Goh ,  Wingshenq Wong

    发明人： Xueren Zhang ,  Kim-Yong Goh ,  Wingshenq Wong

    IPC分类号： H01L23/495 ,  H01L21/44 ,  B23K31/02 ,  B23K37/04

    CPC分类号： H01L24/78 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/14 ,  H01L2924/3025 ,  Y10T29/53265 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015

    摘要： A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.

    摘要翻译： 一种用于在各种包装方法步骤期间最小化可能危及引线框安装件到集成电路管芯封装中的支撑结构的力的装置和方法。 当使用窗夹来在包装期间在引线框接合步骤期间或在引线接合步骤期间提供压力时，由窗夹具施加的垂直力可以通过支撑结构的顶板的物理轮廓在横向方向上传递 。 通过改变支撑结构的顶板的物理轮廓，例如通过设置特定类型的轮廓突起，可以最小化或消除作用于实现引线框架与支撑结构的牢固结合的侧向力。 此外，在引线接合期间，相同的最小化或消除侧向力导致改善的引线接合。