公开(公告)号：US20090230461A1

公开(公告)日：2009-09-17

申请号：US12320620

申请日：2009-01-30

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/792

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y30/00 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114

Abstract: The invention relates a cell device and a cell string for high density flash memory. The cell string includes a plurality of cell devices and switching devices connected to ends of the plurality of cell devices. The cell device includes a semiconductor substrate, an insulating film, a charge storage node composed of nano-sized dots, a control insulating film and a control electrode which are sequentially formed on the semiconductor substrate, without source/drain regions. In the cell string, the silicon substrate enables easy formation of an inversion layer acting as the source/drain regions. The switching device does not include a source or drain region at a side connected to an adjacent cell device but includes a source or drain region at the side opposite to the side connected to the adjacent cell device. The invention improves miniaturizability and performance of cell devices for NAND flash memory, and induces an inversion layer by using a fringing electric field generated from the control electrode and the charge storage node, thus allowing for electrical connection between cells or between cell strings.

Abstract translation: 本发明涉及用于高密度闪速存储器的单元装置和单元串。 单元串包括连接到多个单元装置的端部的多个单元装置和开关装置。 电池器件包括半导体衬底，绝缘膜，由纳米尺寸点组成的电荷存储节点，控制绝缘膜和控制电极，其顺序地形成在半导体衬底上，没有源极/漏极区域。 在电池串中，硅衬底能够容易地形成用作源/漏区的反相层。 开关装置在与相邻电池装置连接的一侧不包括源极或漏极区域，但是在与相邻电池器件连接的一侧相反的一侧包括源极或漏极区域。 本发明提高了NAND​​闪速存储器的单元装置的小型化和性能，并且通过使用从控制电极和电荷存储节点产生的边缘电场来诱导反转层，从而允许单元之间或单元串之间的电连接。

公开(公告)号：US07576395B2

公开(公告)日：2009-08-18

申请号：US11044968

申请日：2005-01-27

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Hwa-Sung Rhee ,  Jae-Kwang Choi

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Hwa-Sung Rhee ,  Jae-Kwang Choi

IPC: H01L23/62

CPC classification number: H01L21/823857 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31645 ,  H01L21/823842 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.

Abstract translation: 集成电路器件包括具有第一掺杂区域和具有与第一掺杂区域不同的掺杂类型的第二掺杂区域的半导体衬底。 半导体衬底上的栅极电极结构在第一和第二掺杂区域之间延伸，并且在第一掺杂区域中具有第一高介电常数材料的栅极绝缘层和不同于第一高介电常数的第二高介电常数材料 材料，在第二掺杂区域。 栅极电极位于栅极绝缘层上。

公开(公告)号：US20090184362A1

公开(公告)日：2009-07-23

申请号：US12314163

申请日：2008-12-05

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/792 ,  G11C11/35

CPC classification number: H01L29/7881 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/792

Abstract: The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, and a transmissive insulating layer, a charge storage node, a control insulating layer and a control electrode sequentially formed on the semiconductor substrate. In the flash memory cell string, a buried insulating layer is provided on the semiconductor substrate between the cell device and an adjacent cell device, thus enabling an inversion layer, which performs the functions of source/drain, to be easily formed.According to the present invention, the reduction characteristics and performance of the cell devices of NAND flash memory are improved, and the inversion layer of a channel is induced through fringing electric fields from the control electrode and the charge storage node if necessary.

Abstract translation: 本发明涉及闪存单元串。 闪存单元串包括连接到单元设备的端部的多个单元设备和交换设备。 每个电池器件包括依次形成在半导体衬底上的半导体衬底和透射绝缘层，电荷存储节点，控制绝缘层和控制电极。 在闪速存储单元串中，在单元装置与相邻单元装置之间的半导体基板上设置掩埋绝缘层，能够容易地形成执行源/漏功能的反转层。 根据本发明，提高了NAND​​闪速存储器的单元装置的还原特性和性能，如果需要，通过来自控制电极和电荷存储节点的边缘电场来感应通道的反转层。

公开(公告)号：US07545626B1

公开(公告)日：2009-06-09

申请号：US12073917

申请日：2008-03-12

Applicant: Dae Hwan Kim ,  Tae Ho Song ,  Hyung Joon Kim ,  Jong Ho Lee ,  Chul Seung Lee

Inventor： Dae Hwan Kim ,  Tae Ho Song ,  Hyung Joon Kim ,  Jong Ho Lee ,  Chul Seung Lee

IPC: H01G4/06

CPC classification number: H01G4/30 ,  H01G4/12 ,  H01G4/255

Abstract: A multi-layer ceramic capacitor including: a ceramic sintered body having cover layers provided on upper and lower surfaces thereof as outermost layers and a plurality of ceramic layers disposed between the cover layers; first and second internal electrodes formed on the ceramic layers, the first and second internal electrodes stacked to interpose one of the ceramic layers; first and second external electrodes formed on opposing sides of the ceramic sintered body to connect to the first and second internal electrodes, respectively; and anti-oxidant electrode layers formed between the cover layers and adjacent ones of the ceramic layers, respectively, the anti-oxidant electrode layers arranged not to affect capacitance.

Abstract translation: 一种多层陶瓷电容器，包括：陶瓷烧结体，其具有在其上表面和下表面上设置为最外层的覆盖层和设置在所述覆盖层之间的多个陶瓷层; 形成在所述陶瓷层上的第一和第二内部电极，所述第一和第二内部电极层叠以插入所述陶瓷层之一; 形成在陶瓷烧结体的相对侧上的第一和第二外部电极分别连接到第一和第二内部电极; 以及在覆盖层和相邻的陶瓷层之间形成的抗氧化剂电极层，抗氧化剂电极层分别布置成不影响电容。

公开(公告)号：US20090115069A1

公开(公告)日：2009-05-07

申请号：US12172912

申请日：2008-07-14

Applicant: Young-Lyong KIM ,  Jong-Ho LEE ,  Min-Ho O

Inventor： Young-Lyong KIM ,  Jong-Ho LEE ,  Min-Ho O

IPC: H01L23/00 ,  H01L21/50 ,  H05K7/00

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/315 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13022 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2224/05599

Abstract: A semiconductor chip package having a molding layer is provided. The semiconductor chip package includes a semiconductor chip, a plurality of external connection terminals, and the molding layer. The semiconductor chip comprises a backside surface, side surfaces, and an active surface having a plurality of chip pads disposed thereon. The molding layer substantially covers the backside surface, the side surfaces, and the active surface of the semiconductor chip and defines at least one opening exposing a portion of the backside surface of the semiconductor chip. A multi-chip package including the semiconductor chip package and a method of manufacturing the semiconductor chip package are also provided.

Abstract translation: 提供具有成型层的半导体芯片封装。 半导体芯片封装包括半导体芯片，多个外部连接端子和成型层。 该半导体芯片包括背面，侧面以及其上设置有多个芯片焊盘的有源表面。 模制层基本上覆盖半导体芯片的背面，侧表面和有源表面，并且限定了暴露半导体芯片背面的一部分的至少一个开口。 还提供了包括半导体芯片封装的多芯片封装和制造半导体芯片封装的方法。

公开(公告)号：US07514310B2

公开(公告)日：2009-04-07

申请号：US11192288

申请日：2005-07-29

Applicant: Min-Joo Kim ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Sungkee Han

Inventor： Min-Joo Kim ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Sungkee Han

IPC: H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/823842

Abstract: A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine.

Abstract translation: 公开了一种半导体器件及相关的制造方法，其中通过用碳和/或氟掺杂金属层，由单一金属层形成双功能金属栅电极。

公开(公告)号：US20080308935A1

公开(公告)日：2008-12-18

申请号：US12141764

申请日：2008-06-18

Applicant: Young-Lyong KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Cheul-Joong YOUN ,  Min-Ho O ,  Tae-Sung YOON ,  Cheol-Joon YOO

Inventor： Young-Lyong KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Cheul-Joong YOUN ,  Min-Ho O ,  Tae-Sung YOON ,  Cheol-Joon YOO

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L21/565 ,  H01L21/566 ,  H01L23/3114 ,  H01L2224/16

Abstract: Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter.

Abstract translation: 提供半导体芯片封装，半导体封装及其制造方法。 在一些实施例中，半导体芯片封装包括包括有源表面，后表面和侧表面的半导体芯片，设置在形成在有源表面上的焊盘上的凸块焊球，以及设置成覆盖有源表面并暴露 凸块焊球的一部分。 相邻凸块焊球之间的成型层可以具有弯月面凹面，其中从活性表面到接触凸块焊球的弯液面凹面的边缘的高度约为相应凸块的最大直径的1/7长度 低于或高于具有最大直径的凸块焊球的部分的焊球。

公开(公告)号：US20080290513A1

公开(公告)日：2008-11-27

申请号：US12125391

申请日：2008-05-22

Applicant: Hyung-Jik BYUN ,  Jong-Gi LEE ,  Jong-Ho LEE ,  Se-Young YANG

Inventor： Hyung-Jik BYUN ,  Jong-Gi LEE ,  Jong-Ho LEE ,  Se-Young YANG

IPC: H01L23/488

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided are a semiconductor package having molded balls on a bottom surface of a PCB and a method of manufacturing the semiconductor package. The semiconductor package includes: a semiconductor chip mounting member comprising circuit patterns on a first surface, an insulating layer defining openings exposing at least portions of the circuit patterns, and external contact terminals arranged on the portions of circuit patterns exposed by the openings; a semiconductor chip formed on a second surface of the semiconductor chip mounting member and electrically connected to the semiconductor chip mounting member; a first sealing portion coating the second surface of the semiconductor chip mounting member and the semiconductor chip; and a second sealing portion arranged on the insulating layer and the external contact terminals such that at least portions of the external contact terminals are exposed.

Abstract translation: 提供了一种在PCB的底表面上具有模制球的半导体封装以及半导体封装的制造方法。 所述半导体封装包括：半导体芯片安装构件，其包括在第一表面上的电路图案，绝缘层限定露出所述电路图案的至少一部分的开口以及布置在由所述开口暴露的所述电路图案部分上的外部接触端子; 半导体芯片，形成在所述半导体芯片安装构件的第二表面上并电连接到所述半导体芯片安装构件; 涂覆半导体芯片安装构件和半导体芯片的第二表面的第一密封部分; 以及布置在绝缘层和外部接触端子上的第二密封部分，使得外部接触端子的至少一部分露出。

公开(公告)号：US20080261360A1

公开(公告)日：2008-10-23

申请号：US12019449

申请日：2008-01-24

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28026 ,  H01L29/49

Abstract: In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.

Abstract translation: 在制造半导体器件的方法中，在包括第一导电类型的第一沟道和不同于第一导电类型的第二导电类型的第二沟道的衬底上形成栅极绝缘层。 在栅极绝缘层上形成包括第一金属的第一导电层，并且在形成在第二沟道上的第一导电层上形成包括不同于第一金属的第二金属的第二导电层。 通过湿式蚀刻工艺部分去除第二导电层，以在第二通道上形成第二导电层图案。

公开(公告)号：US20080217639A1

公开(公告)日：2008-09-11

申请号：US12007495

申请日：2008-01-11

Applicant: Hyun Jun Kim ,  Chang Hwan Choi ,  Won Ha Moon ,  Jong Ho Lee ,  Jae Chul Yong ,  Jin Ha Kim

Inventor： Hyun Jun Kim ,  Chang Hwan Choi ,  Won Ha Moon ,  Jong Ho Lee ,  Jae Chul Yong ,  Jin Ha Kim

IPC: H01L33/00

CPC classification number: H01L33/20 ,  H01L33/46 ,  H01L33/502 ,  H01L33/508 ,  H01L2224/14 ,  H01L2933/0083

Abstract: A photonic crystal light emitting device including: a light emitting diode (LED) light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first and second conductive semiconductor layers; and a first photon-recycling light emitting layer formed on one surface of the first conductive semiconductor layer, opposite to the active layer, wherein the first photon-recycling light emitting layer absorbs a primary light emitted from the LED light emitting structure and emits a light having a different wavelength from that of the primary light, and a photonic crystal structure is formed on an entire thickness of the first photon-recycling light emitting layer.

Abstract translation: 1.一种光子晶体发光器件，包括：发光二极管（LED）发光结构，包括第一导电半导体层，第二导电半导体层和插入在所述第一和第二导电半导体层之间的有源层; 以及形成在与所述有源层相反的所述第一导电半导体层的一个表面上的第一光子再循环发光层，其中所述第一光子再循环发光层吸收从所述LED发光结构发射的初级光，并发射光 具有与初级光的波长不同的波长，并且在第一光子再循环发光层的整个厚度上形成光子晶体结构。