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    POWER-ON-RESET CIRCUIT AND CORRESPONDING ELECTRONIC DEVICE
    261.
    发明申请
    POWER-ON-RESET CIRCUIT AND CORRESPONDING ELECTRONIC DEVICE 有权

    公开(公告)号：US20210297074A1

    公开(公告)日：2021-09-23

    申请号：US17207382

    申请日：2021-03-19

    Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics (Rousset) SAS

    Inventor： Antonino Conte ,  Francesco Tomaiuolo ,  Francesco La Rosa

    IPC: H03K17/22 ,  H03K17/14

    Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

    LOW POWER VOLTAGE REFERENCE CIRCUITS
    262.
    发明申请
    LOW POWER VOLTAGE REFERENCE CIRCUITS 有权

    公开(公告)号：US20210004031A1

    公开(公告)日：2021-01-07

    申请号：US16459169

    申请日：2019-07-01

    Applicant: STMicroelectronics S.r.I.

    Inventor： Marco Orazio Cavallaro ,  Germano Nicollini ,  Giuseppe Palmisano

    IPC: G05F1/46 ,  G05F1/575 ,  G05F1/59

    Abstract: A voltage reference circuit includes a first circuit block configured to generate a proportional to absolute temperature current, the first circuit block comprising a current mirror amplifier, a second circuit block coupled to the first circuit block and configured to generated a complimentary to absolute temperature current, and a third circuit block coupled to both the first circuit block and the second circuit block. The second circuit block includes a multi-stage common-source amplifier. The third circuit block is configured to combine the proportional to absolute temperature current and the complimentary to absolute temperature current to generate a reference voltage at an output of the voltage reference circuit.

    ELECTRONIC CONVERTER AND METHOD OF OPERATING AN ELECTRONIC CONVERTER
    263.
    发明申请
    ELECTRONIC CONVERTER AND METHOD OF OPERATING AN ELECTRONIC CONVERTER 审中-公开

    公开(公告)号：US20200076305A1

    公开(公告)日：2020-03-05

    申请号：US16551984

    申请日：2019-08-27

    Applicant: STMicroelectronics S.r.I. ,  "ALMA MATER STUDIORUM" - UNIVERSITA' DI BOLOGNA

    Inventor： Matteo Pizzotti ,  Michele Dini ,  Aldo Romani ,  Rita Zappa ,  Stefano Corbani ,  Giulio Ricotti

    IPC: H02M3/158 ,  G05F1/52

    Abstract: An electronic converter has first and second input terminals, first and second output terminals, a current regulator circuit arranged between the first input terminal and an intermediate node, and input capacitor arranged between the intermediate node and the second input terminal, and an output capacitor. A control circuit block is configured to sense an input voltage, compare the regulated voltage to a reference value and generate a first signal, compare the input voltage to a lower threshold and an upper threshold and generate a second signal, switch the electronic converter between an active mode and an idle mode as a function of the first signal, and switch the electronic converter between a recharge phase and a switching phase as a function of the second signal when the electronic converter is in the active mode.

    LED DRIVER CIRCUIT, CORRESPONDING DEVICE AND METHOD
    264.
    发明申请
    LED DRIVER CIRCUIT, CORRESPONDING DEVICE AND METHOD 审中-公开

    公开(公告)号：US20190261473A1

    公开(公告)日：2019-08-22

    申请号：US16273661

    申请日：2019-02-12

    Applicant: STMicroelectronics S.r.I.

    Inventor： Ignazio Cala' ,  Santi Carlo Adamo

    IPC: H05B33/08 ,  G06F13/42

    Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes: a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns; an oscillator configured to generate a clock signal for the FSM; a first signal path activatable between the first slave address pin and the FSM; and a second signal path activatable between the FSM and the second slave address pin.

    System and method of determining memory access time
    266.
    发明授权
    System and method of determining memory access time 有权

    公开(公告)号：US10157151B2

    公开(公告)日：2018-12-18

    申请号：US15297897

    申请日：2016-10-19

    Applicant: STMicroelectronics S.r.I

    Inventor： Emanuela Calvetti ,  Marcella Carissimi

    IPC: G06F13/16 ,  G06F13/364 ,  G06F13/42

    Abstract: An embodiment method includes storing, in each of a first plurality of memory locations of a memory, an address of another of the first plurality of memory locations, and reading, from a bus signal received at the memory, an address of a first one of the first plurality of memory locations. The method further includes reading data stored in the first one of the first plurality of memory locations, and determining, using the read data, whether a read error has occurred.

    PIEZOELECTRIC TRANSDUCER FOR AN ENERGY-HARVESTING SYSTEM
    267.
    发明申请
    PIEZOELECTRIC TRANSDUCER FOR AN ENERGY-HARVESTING SYSTEM 审中-公开

    公开(公告)号：US20180198383A1

    公开(公告)日：2018-07-12

    申请号：US15913590

    申请日：2018-03-06

    Applicant: STMicroelectronics S.r.I.

    Inventor： Francesco Procopio ,  Carlo Valzasina ,  Alberto Corigliano ,  Raffaele Ardito ,  Giacomo Gafforelli

    IPC: H02N2/18

    CPC classification number: H02N2/186 ,  H02N2/181 ,  H02N2/188

    Abstract: A piezoelectric transducer for energy-harvesting systems includes a substrate, a piezoelectric cantilever element, a first magnetic element, and a second magnetic element, mobile with respect to the first magnetic element. The first magnetic element is coupled to the piezoelectric cantilever element. The first magnetic element and the second magnetic element are set in such a way that, in response to relative movements between the first magnetic element and the second magnetic element through an interval of relative positions, the first magnetic element and the second magnetic element approach one another without coming into direct contact, and the interaction between the first magnetic element and the second magnetic element determines application of a force pulse on the piezoelectric cantilever element.

    Power management architecture based on microprocessor architecture with embedded and external non-volatile memory
    268.
    发明授权
    Power management architecture based on microprocessor architecture with embedded and external non-volatile memory 有权
    基于具有嵌入式和外部非易失性存储器的微处理器架构的电源管理架构

    公开(公告)号：US09454215B2

    公开(公告)日：2016-09-27

    申请号：US13907543

    申请日：2013-05-31

    Applicant: STMicroelectronics S.r.I.

    Inventor： Alessandro Zafarana

    IPC: G06F1/32 ,  G06F1/26 ,  H02J1/08 ,  G06F12/02 ,  G06F12/12

    CPC classification number: G06F1/3275 ,  G06F1/26 ,  G06F1/32 ,  G06F12/0246 ,  G06F12/12 ,  H02J1/08

    Abstract: A control unit for power supply circuits of points of load (POL) of an electronic system includes a means for autonomous customization by the customer-user of the original control program residing in the ROM of the device, as well as configuration of control parameters of the POL. Microprocessor architecture of the device includes a dedicated logic block and a rewritable non-volatile memory coupled to the data bus of the device or to an auxiliary bus thereof, thus providing a means for software extension of the power supply circuits. RAM is loaded at start-up with data of modified or added routines for implementing new commands and values of configuration and control data of the POL. The RAM may optionally be subjected to encryption/decryption for protection. During operation, program execution jumps from ROM address space to RAM address space and vice versa when certain values of a program counter are reached.

    Abstract translation: 用于电子系统的负载点（POL）的供电电路的控制单元包括客户用户自己定制驻留在设备的ROM中的原始控制程序的装置，以及控制参数的配置 POL。 设备的微处理器架构包括专用逻辑块和耦合到设备的数据总线或其辅助总线的可重写非易失性存储器，从而提供用于电源电路的软件扩展的装置。 RAM在启动时加载了修改或添加的例程的数据，用于实现POL的配置和控制数据的新命令和值。 RAM可以可选地进行加密/解密以进行保护。 在操作过程中，当达到程序计数器的某些值时，程序执行从ROM地址空间跳转到RAM地址空间，反之亦然。

    SYSTEM FOR THE CORRECTION OF AMPLITUDE AND PHASE ERRORS OF IN-QUADRATURE SIGNALS, CORRESPONDING RECEIVER AND METHOD
    269.
    发明申请
    SYSTEM FOR THE CORRECTION OF AMPLITUDE AND PHASE ERRORS OF IN-QUADRATURE SIGNALS, CORRESPONDING RECEIVER AND METHOD 有权
    校正信号的幅度和相位误差的系统，相应的接收器和方法

    公开(公告)号：US20160094379A1

    公开(公告)日：2016-03-31

    申请号：US14751339

    申请日：2015-06-26

    Applicant: STMICROELECTRONICS S.r.I.

    Inventor： Leandro GRASSO ,  Ranieri GUERRA ,  Giuseppe PALMISANO

    IPC: H04L27/38 ,  H04L27/00 ,  G06F17/10

    CPC classification number: H04L27/3836 ,  G06F17/10 ,  H03D3/009 ,  H04L27/0014 ,  H04L27/3863 ,  H04L2027/003

    Abstract: A system may be for the correction of phase and amplitude errors. The system may receive a first input signal and a second input signal and supply a first output signal and a second output signal. The system may include two adders that supply the first and second output signals, respectively. The two adders may be configured for computing a sum of the first and second input signals, and multiplying the weighted sum by a third coefficient. Moreover, the first coefficient or the second coefficient of the first adder may be variable to enable correction of the phase errors, and the third coefficient of the second adder may be variable to enable correction of the amplitude errors.

    Abstract translation: 系统可以用于相位和振幅误差的校正。 系统可以接收第一输入信号和第二输入信号，并提供第一输出信号和第二输出信号。 该系统可以包括分别提供第一和第二输出信号的两个加法器。 两个加法器可以被配置用于计算第一和第二输入信号的和，并将加权和乘以第三系数。 此外，第一加法器的第一系数或第二系数可以是可变的，以使得能够校正相位误差，并且第二加法器的第三系数可以是可变的，以使得校正幅度误差。

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