公开(公告)号：US06897133B2

公开(公告)日：2005-05-24

申请号：US10415425

申请日：2001-10-30

Applicant: Emmanuel Collard

Inventor： Emmanuel Collard

IPC: H01L21/04 ,  H01L29/872 ,  H01L21/28 ,  H01L21/44

CPC classification number: H01L29/6606 ,  H01L21/0455 ,  H01L29/0619 ,  H01L29/872 ,  Y10S438/931

Abstract: The invention concerns a method for making a vertical Schottky diode on a highly doped N-type silicon carbide substrate (1), comprising steps which consist in forming an N-type lightly doped epitaxial layer (2); etching out a peripheral trench at the active zone of the diode; forming a type P doped epitaxial layer; carrying out a planarization process so that a ring (6) of the P type epitaxial layer remains in the trench; forming an insulating layer (3) on the outer periphery of the component, said insulating layer partly covering said ring; and depositing a metal (4) capable of forming a Schottky barrier with the N type epitaxial layer.

Abstract translation: 本发明涉及一种用于在高掺杂N型碳化硅衬底（1）上制造垂直肖特基二极管的方法，包括形成N型轻掺杂外延层（2）的步骤。 在二极管的有源区蚀刻外围沟槽; 形成P型掺杂外延层; 进行平坦化处理，使得P型外延层的环（6）保留在沟槽中; 在所述部件的外周上形成绝缘层（3），所述绝缘层部分覆盖所述环; 以及用N型外延层沉积能够形成肖特基势垒的金属（4）。

公开(公告)号：US20050103987A1

公开(公告)日：2005-05-19

申请号：US10958673

申请日：2004-10-05

Applicant: Remi Brechignac ,  Jonathan Hurwitz

Inventor： Remi Brechignac ,  Jonathan Hurwitz

IPC: H01L31/0203 ,  H01L31/0216 ,  H01L31/0232 ,  H01J5/16

CPC classification number: H01L31/0203 ,  H01L31/02162 ,  H01L31/02325 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A semiconductor component, semiconductor wafer and semiconductor package include an integrated-circuit chip having, on a front face, an optical sensor and electrical connection pads between the edge of this face and this optical sensor. A protective patch made of a transparent material is placed in front of the optical sensor but does not cover the said optical connection pads. The said protective patch is fixed to the front face of the said chip by a bead of an adhesive extending annularly between, and at a certain distance from, the edge of the said optical sensor and of the electrical connection pads. At least one of the faces of the patch is covered with a protective layer of a material that filters out infrared light rays.

Abstract translation: 半导体部件，半导体晶片和半导体封装包括集成电路芯片，其在正面上具有光学传感器和在该面的边缘与该光学传感器之间的电连接焊盘。 由透明材料制成的保护贴片放置在光学传感器的前面，但不覆盖所述光学连接垫。 所述保护贴片通过在所述光学传感器和所述电连接垫的边缘之间并且距离所述光学传感器的边缘和一定距离之间环形延伸的粘合剂珠固定到所述芯片的前表面。 补片的至少一个面被被过滤掉红外光的材料的保护层覆盖。

公开(公告)号：US06893169B1

公开(公告)日：2005-05-17

申请号：US10129371

申请日：2000-10-30

Applicant: Juan Exposito ,  Remi Brechignac

Inventor： Juan Exposito ,  Remi Brechignac

IPC: H01L27/14 ,  H01L25/16 ,  H01L31/02 ,  H01L31/0203 ,  G02B6/36

CPC classification number: H01L31/0203 ,  H01L25/167 ,  H01L2224/05553 ,  H01L2224/48247 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A process is provided for fabricating an optical semiconductor package. According to the process, a first semiconductor component is fixed to a rear face of an electrical connection support plate, and this first component is electrically connected to the support plate. An encapsulation block for the first component is molded on the rear face of the support plate. A second semiconductor component, a front face of which has an optical sensor, is fixed to one face of the first component, and this second component is electrically connected to the support plate. The second component is encapsulated on the front face of the support plate. Also provided is an optical semiconductor package.

Abstract translation: 提供了一种用于制造光学半导体封装的工艺。 根据该过程，第一半导体部件被固定到电连接支撑板的后表面，并且该第一部件电连接到支撑板。 用于第一部件的封装块模制在支撑板的后表面上。 其前表面具有光学传感器的第二半导体部件被固定到第一部件的一个面上，并且该第二部件电连接到支撑板。 第二部件封装在支撑板的前表面上。 还提供了一种光学半导体封装。

公开(公告)号：US20050084052A1

公开(公告)日：2005-04-21

申请号：US10929099

申请日：2004-08-26

Applicant: Bruno Paille

Inventor： Bruno Paille

IPC: H03L7/113 ,  H04L27/00 ,  H04L27/38 ,  H03D3/24

CPC classification number: H04L27/0014 ,  H03L7/113 ,  H04L27/3818 ,  H04L2027/0055 ,  H04L2027/0057 ,  H04L2027/0081

Abstract: A frequency shift of a carrier frequency of an input signal is estimated with a frequency estimator in order to obtain an estimate value. Then, the estimate of the frequency shift is refined, and the carrier frequency is corrected in consequence, with a phase-locked loop that is initialized with the estimate value. The phase-locked loop has a locking frequency range that is narrower than a locking frequency range of the frequency estimator.

Abstract translation: 通过频率估计器来估计输入信号的载波频率的频移，以获得估计值。 然后，改变频移的估计，并且因此利用用估计值初始化的锁相环来校正载波频率。 锁相环具有比频率估计器的锁定频率范围窄的锁定频率范围。

公开(公告)号：US20050082565A1

公开(公告)日：2005-04-21

申请号：US10963383

申请日：2004-10-12

Applicant: Samuel Menard ,  Christophe Mauriac

Inventor： Samuel Menard ,  Christophe Mauriac

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/74 ,  H03K17/722 ,  H01L31/062

CPC classification number: H01L29/42308 ,  H01L29/41716 ,  H01L29/7408 ,  H03K17/722

Abstract: A vertical SCR switch to be controlled by a high-frequency signal having at least four main alternated layers. The switch includes a gate terminal and a gate reference terminal connected via integrated capacitors to corresponding areas. In the case of a thyristor, having on its front surface side a main P-type semiconductor area formed in an N-type gate semiconductor area, a first portion of the main area being connected to one of the main areas, a second portion of the main area is connected to one of the control terminals via a first integrated capacitor, and a portion of the gate area being connected to the other of the control terminals via a second integrated capacitor.

Abstract translation: 垂直SCR开关由具有至少四个主交替层的高频信号控制。 该开关包括通过集成电容器连接到相应区域的栅极端子和栅极参考端子。 在晶闸管的情况下，在其正面侧具有形成在N型栅极半导体区域中的主P型半导体区域，主区域的第一部分连接到主区域之一，第二部分 主区域经由第一集成电容器连接到控制端子之一，并且栅极区域的一部分经由第二集成电容器连接到另一个控制端子。

公开(公告)号：US06882194B2

公开(公告)日：2005-04-19

申请号：US10367195

申请日：2003-02-14

Applicant: Didier Belot ,  Pascal Persechini

Inventor： Didier Belot ,  Pascal Persechini

IPC: G06G7/12 ,  G06G7/16 ,  H03D7/12 ,  H03D7/14 ,  H04B1/707

CPC classification number: H03D7/1425 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0043

Abstract: A differential mixer including at least two input/output stages, each stage including two identical branches, each branch of one of the two stages including at least two bipolar transistors the bases of which define a first pair of input/output terminals of the stage and are connected to a same D.C. current source individually by a respective isolating resistor; the collectors of which define a second pair of input/output terminals of the stage which forms a pair of input/output terminals of another stage of the mixer; and the emitters of which are individually connected to a low voltage reference line by a respective degenerative impedance.

Abstract translation: 包括至少两个输入/输出级的差分混频器，每个级包括两个相同的分支，两级中的一个的每个分支包括至少两个双极型晶体管，其基准基底限定了该级的第一对输入/输出端子，以及 通过相应的隔离电阻器分别连接到相同的DC电流源; 其集电器限定了级的第二对输入/输出端子，其形成混频器的另一级的一对输入/输出端子; 并且其发射极通过相应的退化阻抗单独地连接到低电压参考线。

公开(公告)号：US06879506B2

公开(公告)日：2005-04-12

申请号：US10427713

申请日：2003-05-01

Applicant: Philippe Lebourg ,  Davide Tesi

Inventor： Philippe Lebourg ,  Davide Tesi

IPC: G11C17/10 ,  H01L27/10 ,  G11C17/16 ,  G11C5/02 ,  G11C5/06

CPC classification number: H01L27/101 ,  G11C17/10

Abstract: A memory element in an integrated circuit includes several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an intercalary via level, and at least two connection rails, including several assemblies of successive interconnected areas and vias, a first assembly being formed of a zigzag running from a first metal level to a last metal level and back to the first metal level between a first end and a second end, each of the other assemblies being connected to one of the connection rails, the first end of the zigzag being connected to an initial assembly among the other assemblies.

Abstract translation: 集成电路中的存储元件包括由绝缘电平分开的几层导电材料，每层都能够穿过闰月通孔层的导电通孔，以及包括连续相互连接的区域的多个组件的至少两个连接轨道，以及 通孔，第一组件由从第一金属层到最后金属层之间的之字形形成，并且在第一端与第二端之间回到第一金属层，其它组件中的每一个连接到一个连接轨道 之字形的第一端连接到其他组件之间的初始组件。

公开(公告)号：US06879246B2

公开(公告)日：2005-04-12

申请号：US09853890

申请日：2001-05-11

Applicant: Luc Wuidart

Inventor： Luc Wuidart

IPC: H04B5/02 ,  G06K7/00 ,  H04B1/59 ,  H04Q1/00

CPC classification number: G06K7/10019 ,  G06K7/0008

Abstract: A terminal for generating a high-frequency electromagnetic field by an oscillating circuit, adapted to cooperating with at least one transponder when the transponder enters this field, and a method for establishing a communication between the devices, including circuitry for regulating the signal phase in the oscillating circuit with respect to a reference value and circuitry for evaluating, based on a measurement of the current in the oscillating circuit, the minimum number of transponders present in the field.

Abstract translation: 一种用于通过振荡电路产生高频电磁场的终端，适用于当应答器进入该场时与至少一个应答器协同工作，以及用于建立设备之间的通信的方法，包括用于调节信号相位的电路 振荡电路相对于参考值和电路，用于基于振荡电路中的电流的测量来评估现场中存在的最小转发器数量。

公开(公告)号：US20050071808A1

公开(公告)日：2005-03-31

申请号：US10666725

申请日：2003-09-19

Applicant: Gabriele Luculli

Inventor： Gabriele Luculli

IPC: G06F9/44

CPC classification number: G06F8/73

Abstract: Process for processing an executable embedded software code, said process comprising: reading an executable embedded code for one predetermined processor; extracting code sections from said executable embedded code; reading a file containing a description of a set of instructions for said predetermined processor, based on the concepts of TOKEN, FIELDS, ATTRIBUTES and CONSTRUCTORS of the SLED language, enriched with an additional CLASS definition grouping different instruction under a same label; and using said description in order to derive from said TOKEN, FIELDS, ATTRIBUTES, CONSTRUCTORS and CLASS an internal representation taking the form of a decision tree.

Abstract translation: 用于处理可执行嵌入式软件代码的过程，所述过程包括：读取一个预定处理器的可执行嵌入代码; 从所述可执行嵌入代码提取代码段; 基于SLED语言的TOKEN，FIELDS，ATTRIBUTES和CONSTRUCTORS的概念，读取包含对于所述预定处理器的一组指令的描述的文件，其丰富了在同一标签下对不同指令进行分组的附加CLASS定义; 并且使用所述描述以从所述TOKEN，FIELDS，ATTRIBUTES，CONSTRUCTORS和CLASS得出采用决策树形式的内部表示。

公开(公告)号：US06872996B2

公开(公告)日：2005-03-29

申请号：US10621262

申请日：2003-07-15

Applicant: Nicolas Demange ,  Raffaele Zambrano

Inventor： Nicolas Demange ,  Raffaele Zambrano

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01G7/06

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 在与位线的平行方向上相邻的至少两个单元共享相同的介电区材料和相同的板线。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。