公开(公告)号：US20110156250A1

公开(公告)日：2011-06-30

申请号：US12651365

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L21/565 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto.

Abstract translation: 用于封装封装应用的倒装芯片扇出晶片级封装包括在倒装芯片配置的上表面上具有焊料凸块的半导体管芯。 模具倒置，上表面面向再分布层的上侧，焊料凸块与再分布层的相应芯片接触焊盘电接触。 再分配层包括导电迹线，其将每个焊料凸点与多个上再分布接触焊盘和多个下再分布接触焊盘之一中的一个或两者电接触。 多个上再分配接触垫中的每一个具有与其接触的上焊球。 模具和上焊球至少部分地封装在位于再分配层的上表面上的模具化合物层中，并且其横向尺寸由再分布层的横向尺寸限定。 模具化合物层具有背面表面，每个上焊球的一部分暴露在其中，用于与上封装电接触。 每个下再分布接触垫具有与其耦合的较低焊球。

公开(公告)号：US20110156239A1

公开(公告)日：2011-06-30

申请号：US12649118

申请日：2009-12-29

Applicant: Yonggang Jin

Inventor： Yonggang Jin

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L23/5389 ,  H01L21/78 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for manufacturing a fan-out embedded panel-level package. Film having an adhesive on each side is applied to the non-active face of a plurality of semiconductor die while the die are still in wafer form. The die are singulated from the wafer and placed on a carrier, using the adhesive on the unused side of the film to attach the die to the carrier. Encapsulant material is dispensed onto the carrier adjacent to the die, providing an exposed surface on the encapsulant material approximately even with the active faces of the die. Elements of the redistribution layer such as conductors and fan-out pads are applied to this surface. A solder ball array is placed on the fan-out pads and then the die are re-singulated by cutting through the encapsulation material and the carrier, yielding individual electronic packages.

Abstract translation: 一种用于制造扇出嵌入式面板级封装的方法。 当模具仍然是晶片形式时，在各个侧面上具有粘合剂的膜被施加到多个半导体管芯的非活性面。 将晶片从晶片上分离并放置在载体上，使用薄膜的未使用侧上的粘合剂将模具附着到载体上。 将封装材料分配到与模具相邻的载体上，在密封剂材料上提供大致均匀的模具的活性面的暴露表面。 再分配层的元件如导体和扇出垫被施加到该表面。 将焊球阵列放置在扇出焊盘上，然后通过切割封装材料和载体来重新分割裸片，产生单独的电子封装。

公开(公告)号：US20110156033A1

公开(公告)日：2011-06-30

申请号：US12651389

申请日：2009-12-31

Applicant: Yohanes Bintang ,  Enghsiung Ng

Inventor： Yohanes Bintang ,  Enghsiung Ng

IPC: H01L23/544 ,  H01L21/56 ,  H01L21/50 ,  H01L21/66 ,  G06F17/30

CPC classification number: H01L23/544 ,  G01R31/26 ,  H01L21/568 ,  H01L21/67294 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68372 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/83 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method and system for tracing die at unit level, comprising: assigning a first identification to a support member including a plurality of die support units; generating a second identification corresponding to a die support unit, the second identification including the first identification and a coordinate of the die support unit within the support member; correlating the second identification to a third identification of a die; attaching the die to the die support unit to generate a packaged die; and assigning the second identification to the packaged die.

Abstract translation: 一种用于在单元级跟踪模具的方法和系统，包括：将第一标识分配给包括多个模具支撑单元的支撑构件; 产生对应于模具支撑单元的第二识别，所述第二识别包括所述支撑构件内的所述模具支撑单元的所述第一识别和坐标; 将第二识别与模具的第三标识相关联; 将管芯附接到管芯支撑单元以产生封装的管芯; 以及将所述第二标识分配给所述封装的模具。

公开(公告)号：US20110147191A1

公开(公告)日：2011-06-23

申请号：US12641793

申请日：2009-12-18

Applicant: Sebastien Marsanne ,  Boon Nam Poh ,  Samuel Devanandan

Inventor： Sebastien Marsanne ,  Boon Nam Poh ,  Samuel Devanandan

IPC: H03K17/975 ,  G01R31/02

CPC classification number: G01R31/2818

Abstract: Composite materials having conductive properties are described for use in testing circuits and in manufacturing electrical switches. The composite materials described, when in an unstressed state, generally behave as insulators. However, when sufficient mechanical pressure is applied to portions of the composite materials, the portions to which the mechanical pressure is applied become increasingly conductive. Methods for testing a PCB using composite material switches are also disclosed. A sheet that includes a composite material may be used to test electrical functionality of various regions on a PCB by way of local pressure application. The sheet may be easily applied to and removed from the PCB. Additionally, in forming an electrical switch, a voltage applied to one or more actuating elements may be used to provide mechanical pressure to a composite material that is disposed between two conductive members. Application of a sufficient voltage allows for portions of the composite material to transition from an insulator to a conductor for providing an electrical pathway.

Abstract translation: 描述了具有导电特性的复合材料用于测试电路和制造电气开关。 当处于无应力状态时，描述的复合材料通常表现为绝缘体。 然而，当对复合材料的部分施加足够的机械压力时，施加机械压力的部分变得越来越导电。 还公开了使用复合材料开关测试PCB的方法。 包括复合材料的片材可以用于通过局部压力应用来测试PCB上各个区域的电学功能。 该片材可以容易地应用于PCB并从PCB上移除。 另外，在形成电气开关时，施加到一个或多个致动元件的电压可以用于向布置在两个导电构件之间的复合材料提供机械压力。 施加足够的电压允许复合材料的部分从绝缘体转移到导体以提供电路径。

公开(公告)号：US20110032021A1

公开(公告)日：2011-02-10

申请号：US12537505

申请日：2009-08-07

Applicant: Guo Dianbo

Inventor： Guo Dianbo

IPC: H03K17/687 ,  H03K17/56

CPC classification number: H03K17/063 ,  H03K2017/066

Abstract: An analog T switch is disclosed which has high isolation in the off state. The analog T switch can include series-connected NMOS transistors having separate gate control. The gates of the NMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog switch can include series-connected PMOS transistors having separate gate control. The gates of the PMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog T switch can include a substrate voltage control circuit that controls the voltage of the substrate regions in which the PMOS transistors are formed. The substrate voltage control circuit can isolate the substrate regions of the PMOS transistors from one another in the off state to improve off state isolation of the analog T switch.

Abstract translation: 公开了一种在关闭状态下具有高隔离度的模拟T开关。 模拟T开关可以包括具有分离的栅极控制的串联连接的NMOS晶体管。 NMOS晶体管的栅极可以彼此隔离，以改善模拟T开关的截止状态隔离。 模拟开关可以包括具有分离的栅极控制的串联连接的PMOS晶体管。 PMOS晶体管的栅极可以彼此隔离，以改善模拟T开关的截止状态隔离。 模拟T开关可以包括控制其中形成PMOS晶体管的衬底区域的电压的衬底电压控制电路。 衬底电压控制电路可以在关断状态下将PMOS晶体管的衬底区域彼此隔离，以改善模拟T开关的截止状态隔离。

公开(公告)号：US07877236B2

公开(公告)日：2011-01-25

申请号：US11881507

申请日：2007-07-27

Applicant: Donghyun Seo ,  Kijun Nam ,  Seokseong Yoon

Inventor： Donghyun Seo ,  Kijun Nam ,  Seokseong Yoon

IPC: H03K19/00 ,  G06F11/00

CPC classification number: H03K5/086 ,  G01R31/30 ,  G01R31/3004 ,  G01R31/318357

Abstract: An integrated circuit includes a first storage location, a first generator, a converter, and a second generator. The first storage location is operable to store a first adjustment value. The first generator is coupled to the first storage location, is operable to generate a first signal having a first characteristic, and includes a first adjuster operable to change the first characteristic in response to the first adjustment value. The converter is coupled to the first storage location and is operable to generate from the first adjustment value a modified adjustment value. The second generator is coupled to the converter, is operable to generate a second signal having a second characteristic, and includes a second adjuster operable to change the second characteristic in response to the modified adjustment value.

Abstract translation: 集成电路包括第一存储位置，第一发生器，转换器和第二发生器。 第一存储位置可操作以存储第一调整值。 第一发生器耦合到第一存储位置，可操作以产生具有第一特性的第一信号，并且包括可操作以响应于第一调整值改变第一特性的第一调节器。 转换器耦合到第一存储位置，并且可操作以从第一调整值生成修改的调整值。 第二发生器耦合到转换器，可操作以产生具有第二特性的第二信号，并且包括可响应修改的调整值改变第二特性的第二调节器。

公开(公告)号：US20100187651A1

公开(公告)日：2010-07-29

申请号：US12578382

申请日：2009-10-13

Applicant: Yonggang JIN ,  Kiyoshi Kuwabara ,  Xavier Baraton

Inventor： Yonggang JIN ,  Kiyoshi Kuwabara ,  Xavier Baraton

IPC: H01L23/495 ,  H01L27/06 ,  H01L21/50

CPC classification number: H01L24/83 ,  H01L21/311 ,  H01L21/4821 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/18 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/8385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

Abstract: Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.

Abstract translation: 本发明的方面涉及一种集成电路封装及其形成方法，更具体地涉及用于集成电路的重新分配的芯片封装。 集成电路封装包括在集成电路的至少一部分上具有保护材料的集成电路。 引线框架耦合到集成电路，并且导电层也耦合到互连。 焊球与导电层耦合，钝化层位于导电层上。 有源和无源部件电耦合到集成电路。

公开(公告)号：US07705912B2

公开(公告)日：2010-04-27

申请号：US10795796

申请日：2004-03-08

Applicant: Jianhua Sun ,  Sapna George

Inventor： Jianhua Sun ,  Sapna George

IPC: H04N7/12 ,  G10L19/00

CPC classification number: G11B20/10527 ,  G10L19/00 ,  G11B2020/10546 ,  H04N5/9267

Abstract: A method of decoding audio data, encoded in multiple DIF blocks in a Digital Video (DV) data stream, and outputting said audio data as a PCM frame, includes fetching a single Digital Interface Frame (DIF) block from the DV data stream. A first byte in the single DIF block is de-shuffled to determine its index (n) in the PCM frame. Each byte in the in the single DIF block is de-shuffled to determine its respective index (n) in the PCM frame. The de-shuffled data is written into the PCM frame for output if the present DIF block is the last in the present DV frame. Subsequent DIF blocks in the DV frame are processed in the manner described above.

Abstract translation: 在数字视频（DV）数据流中以多个DIF块编码的音频数据进行解码，并将该音频数据作为PCM帧输出的方法包括从DV数据流中取出单个数字接口帧（DIF）块。 单个DIF块中的第一个字节被去混洗，以确定其在PCM帧中的索引（n）。 在单个DIF块中的每个字节被去混洗以确定其在PCM帧中的相应索引（n）。 如果当前DIF块是当前DV帧中的最后一个，则将混洗后的数据写入PCM帧中以进行输出。 DV帧中的随后的DIF块以上述方式进行处理。

公开(公告)号：US20100098198A1

公开(公告)日：2010-04-22

申请号：US12579935

申请日：2009-10-15

Applicant: Karthik MURALIDHAR ,  George A. Vlantis

Inventor： Karthik MURALIDHAR ,  George A. Vlantis

IPC: H04B1/10 ,  H04L27/00

CPC classification number: H04L25/022 ,  H04L25/0244 ,  H04L25/03821 ,  H04L27/2601

Abstract: In an embodiment, a multi-carrier signal (e.g., an OFDM signal) is received over a channel. Indicators of interference and the channel response at a carrier frequency of the signal are determined, and compared. If the indicator of interference has a particular relationship to the indicator of the channel response, then a data value transmitted at the carrier frequency is recovered from a data value received at the carrier frequency according to a particular data-recovery algorithm. Because the particular data-recovery algorithm may be faster than a conventional data-recovery algorithm, recovering one or more data values with the particular algorithm may increase the speed at which data is recovered from a multicarrier signal as compared to using a conventional data-recovery algorithm.

Abstract translation: 在一个实施例中，通过信道接收多载波信号（例如，OFDM信号）。 确定信号载波频率处的干扰指标和信道响应，并进行比较。 如果干扰指示符与信道响应的指示符具有特定的关系，则根据特定的数据恢复算法从载波频率接收的数据值恢复在载波频率处发送的数据值。 由于特定的数据恢复算法可能比传统的数据恢复算法更快，与使用常规数据恢复相比，用特定算法恢复一个或多个数据值可能会增加数据从多载波信号中恢复的速度 算法。

公开(公告)号：US07660718B2

公开(公告)日：2010-02-09

申请号：US10948950

申请日：2004-09-23

Applicant: Kabi Prakash Padhi ,  Sapna George

Inventor： Kabi Prakash Padhi ,  Sapna George

IPC: G10L13/00

CPC classification number: G10L25/90

Abstract: Pitch detection of speech signals finds numerous applications in karaoke, voice recognition and scoring applications. While most of the existing techniques rely on time domain methods, the invention utilizes frequency domain methods. There is provided a method and system for determining the pitch of speech from a speech signal. The method includes the steps of: producing or obtaining the speech signal; distinguishing the speech signal into voiced, unvoiced or silence sections using speech signal energy levels; applying a Fourier Transform to the speech signal and obtaining speech signal parameters; determining peaks of the Fourier transformed speech signal; tracking the speech signal parameters of the determined peaks to select partials; and determining the pitch from the selected partials using a two-way mismatch error calculation.

Abstract translation: 语音信号的间距检测在卡拉OK，语音识别和评分应用中发现了许多应用。 虽然大多数现有技术依赖于时域方法，但本发明利用频域方法。 提供了一种用于从语音信号确定语音音调的方法和系统。 该方法包括以下步骤：产生或获得语音信号; 使用语音信号能级将语音信号区分成有声，无声或静音部分; 对所述语音信号应用傅立叶变换并获得语音信号参数; 确定所述傅里叶变换语音信号的峰值; 跟踪确定的峰值的语音信号参数以选择部分; 以及使用双向错配误差计算从所选择的部分中确定音高。