ENCRYPTING DATA UNITS WITH A MEMRISTOR ARRAY
    282.
    发明公开

    公开(公告)号:US20230208612A1

    公开(公告)日:2023-06-29

    申请号:US17563814

    申请日:2021-12-28

    Inventor: AMIT S. SHARMA

    CPC classification number: H04L9/0631

    Abstract: Systems and methods are provided for encrypting data in a memristor array. The data may be scrambled by multiplying an input data unit by another data unit, by multiplying each element of a first data unit by a different instance of a second data unit. The process continues until all elements of the first data unit are multiplied by a different instance of the second data unit. The elements of the data units may be represented by resistive values of a memristor array. The result of all of the above multiplication of different instances of the second data unit are a new set of data units. All of the resulting data units are added together by adding the currents associated with values of the memristors representing the resulting data units. The operation may be performed as a finite field computation, with the memristor array.

    Method and system for dynamic topology-aware space allocation in a distributed system

    公开(公告)号:US11687272B2

    公开(公告)日:2023-06-27

    申请号:US17359080

    申请日:2021-06-25

    CPC classification number: G06F3/0655 G06F3/064 G06F3/0604 G06F3/067

    Abstract: A system divides non-volatile memory of a plurality of storage devices into physical extents which comprises chunks. The system allocates slabs associated with the storage devices, wherein a respective slab comprises extents from different storage devices and further comprises stripes. A stripe comprises a chunk from each extent of the respective slab. The system updates, in a first data structure, an entry which indicates: a slab number for the respective allocated slab; and a storage device identifier and an extent number for each extent in the respective allocated slab. Responsive to receiving a write request, the system obtains a first stripe from a pre-allocated list which includes the allocated slabs. The system searches, based on stripe information associated with the first stripe, the first data structure to obtain a physical location in a storage device to which to issue the write request.

    ACCUMULATORS CORRESPONDING TO BINS IN MEMORY
    289.
    发明公开

    公开(公告)号:US20230185721A1

    公开(公告)日:2023-06-15

    申请号:US17644352

    申请日:2021-12-15

    CPC classification number: G06F12/0848 G06F2212/608

    Abstract: In some examples, a system includes a processing entity and a memory to store data arranged in a plurality of bins associated with respective key values of a key. The system includes a cache to store cached data elements for respective accumulators that are updatable to represent occurrences of the respective key values of the key, where each accumulator corresponds to a different bin of the plurality of bins, and each cached data element has a range that is less than a range of a corresponding bin of the plurality of bins. Responsive to a value of a given cached data element as updated by a given accumulator satisfying a criterion, the processing entity is to cause an aggregation of the value of the given cached data element with a bin value in a respective bin.

    Control circuit for bridge MOSFETs
    290.
    发明授权

    公开(公告)号:US11677314B2

    公开(公告)日:2023-06-13

    申请号:US17511422

    申请日:2021-10-26

    CPC classification number: H02M1/4225 H02M1/4233 H02M3/1582 H02M7/219

    Abstract: A control circuit for a plurality of metal-oxide semiconductor field-effect transistors (MOSFETs) in a bridge circuit for rectifying an alternating current (AC) input to generate a direct-current (DC) output includes first and second high side controls and first and second low side controls for providing gate voltage signals to respective MOSFETs in the bridge circuit. Dead time controls are provided for establishing dead time intervals between activation of complementary MOSFETs in the bridge circuit. The low side controls provide gate voltage signals having sloped edges and the dead time controls include Zener diodes having reverse bias thresholds for determining the duration of the dead time intervals.

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