公开(公告)号：US06194748B1

公开(公告)日：2001-02-27

申请号：US09303959

申请日：1999-05-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating an integrated circuit with less susceptibility to gate-edge fringing field effect is disclosed. The transistor includes a low-k dielectric spacer and a high-k gate dielectric. The high-k gate dielectric can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).

Abstract translation: 公开了一种制造具有对边缘边缘场效应较不敏感的集成电路的方法。 晶体管包括低k电介质隔离物和高k栅极电介质。 高k栅极电介质可以是五氧化钽或二氧化钛。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06180499B2

公开(公告)日：2001-01-30

申请号：US09162917

申请日：1998-09-29

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L29/4966 ,  H01L21/2807 ,  H01L21/32105 ,  H01L21/32155 ,  H01L21/823828

Abstract: A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a comparatively low dose, and then oxidizing the doped polysilicon layer. Under the influence of the oxidation, the germanium is repelled from an upper sacrificial region of the polysilicon layer into a lower gate region of the polysilicon layer, thereby increasing the germanium concentration in the lower gate region. The sacrificial region is then etched away and an undoped polysilicon film deposited on the gate region. Subsequently, the gate region with undoped polysilicon film is patterned to establish a MOSFET gate, with the substrate then being appropriately processed to establish MOSFET source/drain regions.

Abstract translation: 制造ULSI MOSFET芯片的方法包括在衬底上形成晶体管栅极。 栅极通过在衬底上沉积多晶硅层，以比较低的剂量将锗注入到多晶硅层中，然后氧化掺杂的多晶硅层而形成。 在氧化的影响下，锗从多晶硅层的上部牺牲区域排斥到多晶硅层的下部栅极区域，从而增加下部栅极区域中的锗浓度。 然后蚀刻掉牺牲区域，并且在栅极区域上沉积未掺杂的多晶硅膜。 随后，对具有未掺杂多晶硅膜的栅极区域进行构图以建立MOSFET栅极，然后适当地处理衬底以建立MOSFET源极/漏极区域。

公开(公告)号：US6114206A

公开(公告)日：2000-09-05

申请号：US187171

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/82345

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV. A damascene process can be utilized to fabricate the MOSFETs.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET包括具有多晶硅材料的栅极结构。 用较低浓度的锗注入多晶硅材料，其中需要较低的阈值电压MOSFET。 在锗的0-60％浓度范围内，阈值电压可以改变大约240mV。 可以使用镶嵌工艺来制造MOSFET。

公开(公告)号：US6100120A

公开(公告)日：2000-08-08

申请号：US309928

申请日：1999-05-11

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L22/00 ,  H01L21/84

CPC classification number: H01L21/28211 ,  H01L21/28229 ,  H01L29/517 ,  H01L29/66583

Abstract: A method of forming a dielectric gate insulator in a transistor is disclosed herein. The method includes depositing a layer of material over a semiconductor structure; depositing a covering layer over the layer of material; selectively creating an aperture in the covering layer, wherein an area of the layer of material is exposed; providing thermal oxidation to the exposed area of the layer of material to produce an oxidized area; providing a gate over the oxidized area; and removing the covering layer.

Abstract translation: 本文公开了在晶体管中形成电介质栅极绝缘体的方法。 该方法包括在半导体结构上沉积材料层; 在所述材料层上沉积覆盖层; 选择性地在所述覆盖层中产生孔，其中所述材料层的区域被暴露; 向所述材料层的暴露区域提供热氧化以产生氧化区域; 在氧化区域上设置一个门; 并去除覆盖层。

公开(公告)号：US6084271A

公开(公告)日：2000-07-04

申请号：US187892

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

公开(公告)号：US5985726A

公开(公告)日：1999-11-16

申请号：US187635

申请日：1998-11-06

Applicant: Bin Yu ,  Judy Xilin An

Inventor： Bin Yu ,  Judy Xilin An

IPC: H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66492 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dummy or sacrificial gate structure. Dopants are provided through the openings associated with sacrificial spacers to form the source and drain extensions. The openings can be filled with spacers The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用虚拟或牺牲栅极结构。 通过与牺牲间隔物相关联的开口提供掺杂剂以形成源极和漏极扩展。 开口可以填充间隔物该工艺可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US5880511A

公开(公告)日：1999-03-09

申请号：US497079

申请日：1995-06-30

Applicant: Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

Inventor： Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

IPC: H01L29/861 ,  H01L29/866

CPC classification number: H01L29/8618 ,  H01L29/861 ,  H01L29/866

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.0E17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 um. The thickness of the third (p+) region should be between about 0.3 um and about 2.0 um, and the thickness of the second (p-) region should be between about 0.5 um and about 5.0 um.

Abstract translation: 穿通二极管瞬态抑制器件具有改变掺杂浓度的基极区域，以改善泄漏和钳位特性。 穿通二极管包括包括n +区域的第一区域，包括邻接第一区域的p-区域的第二区域，包括邻接第二区域的p +区域的第三区域，以及包括邻接第三区域的n +区域的第四区域 地区。 n +层的峰值掺杂剂浓度应为约1.5E18cm-3，p +层的峰值掺杂剂浓度应在n +层的峰值浓度的约1至约5倍之间， 层应在约0.5E14cm-3和约1.0E17cm-3之间。 第四（n +）区域的结深度应大于约0.3μm。 第三（p +）区域的厚度应在约0.3μm至约2.0μm之间，第二（p-）区域的厚度应在约0.5μm至约5.0μm之间。

公开(公告)号：US09326250B2

公开(公告)日：2016-04-26

申请号：US14240896

申请日：2012-06-06

Applicant: Zhirong Lin ,  Bo Dai ,  Bin Yu ,  Lu Ren

Inventor： Zhirong Lin ,  Bo Dai ,  Bin Yu ,  Lu Ren

IPC: H04L1/00 ,  H04W52/14 ,  H04L5/00 ,  H04W52/34

CPC classification number: H04W52/146 ,  H04L5/0042 ,  H04W52/34

Abstract: The present disclosure provides a method for reducing the transmission power of an uplink signal, comprising: performing, by a User Equipment (UE), Component Carrier (CC) grouping on configured uplink CCs; and comparing correspondingly the transmission power of an uplink signal in each CC group with a maximum transmission power configured for the each CC group by an evolved Node B (eNB), and performing a power reduction within the CC group when the comparison result meets an intra-group power reduction condition; and/or comparing the sum of transmission powers of uplink signals in all CC groups with a maximum transmission power configured for the UE by the eNB, when the comparison result meets an inter-group power reduction condition, performing a power reduction between the CC groups. The present disclosure further provides a device for reducing the transmission power of an uplink signal. The technical solution of the present disclosure can improve the covering capability and reliability of the uplink signal in an Inter-band CA scenario, and to improve a utilization rate of a UE's uplink transmission power.

Abstract translation: 本公开提供了一种用于降低上行链路信号的发送功率的方法，包括：由用户设备（UE）执行在配置的上行链路CC上的分量载波（CC）分组; 并对每个CC组中的上行链路信号的发送功率与由演进节点B（eNB）为每个CC组配置的最大发送功率进行比较，并且当比较结果满足帧内时，执行CC组内的功率降低 - 组功率降低条件; 和/或将所有CC组中的上行链路信号的发送功率之和与eNB配置的最大发送功率进行比较，当比较结果满足组间功率降低条件时，在CC组之间进行功率降低 。 本公开还提供了一种用于降低上行链路信号的发射功率的装置。 本公开的技术方案可以提高带间CA方案中上行链路信号的覆盖能力和可靠性，并提高UE上行传输功率的利用率。

公开(公告)号：US09282549B2

公开(公告)日：2016-03-08

申请号：US13824085

申请日：2011-06-30

Applicant: Bo Dai ,  Shuqiang Xia ,  Chunli Liang ,  Bin Yu

Inventor： Bo Dai ,  Shuqiang Xia ,  Chunli Liang ,  Bin Yu

IPC: H04W72/04 ,  H04L1/00 ,  H04L1/16 ,  H04L1/18

CPC classification number: H04W72/0413 ,  H04L1/0026 ,  H04L1/0028 ,  H04L1/1671 ,  H04L1/1861 ,  H04L5/001 ,  H04L5/0016 ,  H04L5/0044 ,  H04L5/0048 ,  H04L5/0053

Abstract: A method for transmitting feedback information and a user equipment are disclosed in the present document, wherein, one method includes: a User Equipment (UE) performing time domain extension on feedback information within one subframe; and mapping respectively data which go through the time domain extension and demodulation reference signals corresponding to the data which go through the time domain extension to multiple uplink Single Carrier-Frequency Division Multiple Access (SC-FDMA) symbols within the subframe, and transmitting the data which go through the time domain extension and the demodulation reference signals corresponding to the data which go through the time domain extension in the same frequency domain position in a way of time division multiplexing; wherein, each uplink SC-FDMA symbol occupies n successive physical resource blocks in the frequency domain, and n is a positive integer.

Abstract translation: 在本文中公开了一种用于发送反馈信息和用户设备的方法，其中一种方法包括：在一个子帧内对反馈信息执行时域扩展的用户设备（UE） 并分别将通过时域扩展的数据对应的时域扩展和解调参考信号的数据映射到子帧内的多个上行链路单载波 - 频分多址（SC-FDMA）符号，并发送数据 其以时分复用方式通过时域扩展和对应于通过时域扩展的数据的解调参考信号在同一频域位置; 其中，每个上行链路SC-FDMA符号占据频域中的n个连续的物理资源块，并且n是正整数。

公开(公告)号：US09220091B2

公开(公告)日：2015-12-22

申请号：US13817478

申请日：2011-07-22

Applicant: Weiwei Yang ,  Bo Dai ,  Chunli Liang ,  Shuqiang Xia ,  Bin Yu

Inventor： Weiwei Yang ,  Bo Dai ,  Chunli Liang ,  Shuqiang Xia ,  Bin Yu

IPC: H04W72/04 ,  H04L1/00 ,  H04L1/16

CPC classification number: H04W72/0413 ,  H04L1/0026 ,  H04L1/0071 ,  H04L1/0072 ,  H04L1/1671

Abstract: The disclosure discloses a method and terminal for transmitting uplink control information. The method includes: coding the uplink control information required to be transmitted and data information corresponding to one or two transport blocks respectively, obtaining an encoded sequence according to a target length, and forming a corresponding coded modulation sequence from the encoded sequence according to a modulation mode (401); interleaving the obtained coded modulation sequence, and transmitting the interleaved coded modulation sequence on a layer corresponding to a Physical Uplink Shared Channel (PUSCH) (402). By adopting the method and terminal according to the disclosure the transmission of uplink control information with greater bits on the PUSCH is realized. The disclosure also provides a method for determining a number of code symbols required in each layer when transmitting uplink control information on the PUSCH, thus the purpose of determining a number of code symbols required in each layer when transmitting uplink control information on the PUSCH is realized.

Abstract translation: 本公开公开了一种用于发送上行链路控制信息的方法和终端。 该方法包括：分别对需要发送的上行链路控制信息和对应于一个或两个传输块的数据信息进行编码，根据目标长度获得编码序列，并根据编码序列形成相应的编码调制序列 模式（401）; 交织所获得的编码调制序列，并且在与物理上行链路共享信道（PUSCH）（402）相对应的层上发送交织的编码调制序列。 通过采用根据本公开的方法和终端，实现在PUSCH上具有更大比特的上行链路控制信息的传输。 本公开还提供了一种用于在PUSCH上发送上行链路控制信息时确定每层中所需的码元数量的方法，从而实现了在PUSCH上发送上行控制信息时确定每层中所需的码符号数目的目的 。