公开(公告)号：US09093161B2

公开(公告)日：2015-07-28

申请号：US13830207

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

Abstract translation: 公开了用于编程高级纳米闪存单元的改进的方法和装置。

公开(公告)号：US20150155039A1

公开(公告)日：2015-06-04

申请号：US14094595

申请日：2013-12-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC: G11C16/08

CPC classification number: G11C16/08 ,  G11C7/1045 ,  G11C7/1057 ,  G11C16/04 ,  G11C2207/105 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157

Abstract: A three-dimensional NOR flash memory system is disclosed. The system optionally comprises configurable standard pins, a configurable output buffer, and a configurable input buffer.

Abstract translation: 公开了一种三维NOR闪存系统。 该系统可选地包括可配置标准引脚，可配置输出缓冲器和可配置输入缓冲器。

公开(公告)号：US20140226409A1

公开(公告)日：2014-08-14

申请号：US14257335

申请日：2014-04-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.

Abstract translation: 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压，并由接收第一电压的电压调节器产生。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 电压调节器由控制器使能。

公开(公告)号：US20140198568A1

公开(公告)日：2014-07-17

申请号：US14140452

申请日：2013-12-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Sakhawat M. Khan

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/005 ,  G11C2211/5634

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract translation: 为数字多位非易失性存储器集成系统提供高速电压模式感测。 一个实施例具有本地源跟随器阶段，之后是高速公共源级。 另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。 另一个实施例具有公共源级，之后是源跟随器。 使用自动归零方案。 使用电容感测方案。 描述多级并行操作。

公开(公告)号：US20130235664A1

公开(公告)日：2013-09-12

申请号：US13866966

申请日：2013-04-19

Applicant: SILICON STORAGE TECHNOLOGY INC.

Inventor： Hieu Van Tran ,  Sakhawat M. KHAN

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/005 ,  G11C2211/5634

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract translation: 为数字多位非易失性存储器集成系统提供高速电压模式感测。 一个实施例具有本地源跟随器阶段，之后是高速公共源级。 另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。 另一个实施例具有公共源级，之后是源跟随器。 使用自动归零方案。 使用电容感测方案。 描述多级并行操作。

公开(公告)号：US20250165342A1

公开(公告)日：2025-05-22

申请号：US19033427

申请日：2025-01-21

Applicant: Silicon Storage Technology, inc.

Inventor： Hieu Van Tran

IPC: G06F11/10

Abstract: Numerous examples are disclosed of an improved grouping and error correction system for non-volatile memory cells. In one example, a system comprises a memory array comprising non-volatile memory cells arranged into rows and columns, wherein the array stores a plurality of words, wherein respective words are divided into multiple sub-words and respective non-volatile memory cells in the memory array store digital bits belonging to different sub-words of the plurality of sub-words.

公开(公告)号：US12217165B2

公开(公告)日：2025-02-04

申请号：US17190376

申请日：2021-03-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C16/24 ,  G06N3/065 ,  G11C11/40 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26

Abstract: Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed. In some embodiments, concurrent operations occur among different banks of memory. In other embodiments, concurrent operations occur among different blocks of memory, where each block comprises two or more banks of memory. The embodiments substantially reduce the timing overhead for weight writing and verifying operations in analog neural memory systems.

公开(公告)号：US12205655B2

公开(公告)日：2025-01-21

申请号：US17841411

申请日：2022-06-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G06F3/06 ,  G06N3/063 ,  G06N3/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/10

Abstract: In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

公开(公告)号：US12124944B2

公开(公告)日：2024-10-22

申请号：US17185725

申请日：2021-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Mark Reiten

IPC: G06N3/065 ,  G06F17/16

CPC classification number: G06N3/065 ,  G06F17/16

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US12099921B2

公开(公告)日：2024-09-24

申请号：US17367633

申请日：2021-07-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/065 ,  G06F17/16 ,  G06N3/04

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.