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公开(公告)号：US12019716B2
公开(公告)日：2024-06-25
申请号：US16661894
申请日：2019-10-23
发明人： Yong Li , Xuemin Chen , Brett Tischler , Prashant Katre
IPC分类号： G06Q30/00 , G06F18/22 , G06F18/28 , G06F21/12 , G06F21/16 , G06N5/04 , G06N20/00 , G06V10/772 , G06V20/40
CPC分类号： G06F21/16 , G06F18/22 , G06F18/28 , G06F21/125 , G06N5/04 , G06N20/00 , G06V10/772 , G06V20/46
摘要： A system for multimedia content recognition includes a cloud server and a media client including a silicon-on-chip (SoC) device to communicate with the cloud server via a network. The SoC device includes a local area network (LAN) interface to receive media content from a media source and a media monitor to analyze the received media content and to generate signature information for transmission to the cloud server or for a local analysis. The SoC device further includes an inference engine to locally analyze the signature information to detect an unauthorized access.
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公开(公告)号：US20240194189A1
公开(公告)日：2024-06-13
申请号：US18077180
申请日：2022-12-07
摘要： An electronic device includes a far-field voice (FFV) processor including a source selection module. The source selection module receives a set of audio signals and determines, for each audio stream, whether the audio stream is relevant to an application. The source selection module receives several separate probability computations, with each probability computation providing a probability of the presence of a particular characteristic. Additionally, the source selection module receives one or more applications as well relevance information (e.g., one or relevant characteristics) associated with the one or applications. The source selection module can used respective probabilities to determine if one or more characteristics are present in an audio signal, and compare the characteristic(s) to the relevance information for the application. Using this information, the source selection module can determine, for each audio signal, to which respective application the audio stream is relevant.
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公开(公告)号：US12002741B2
公开(公告)日：2024-06-04
申请号：US17536298
申请日：2021-11-29
发明人： Michael Leary , Ah Ron Lee , Chris Chung , YongIk Choi , Domingo Figueredo
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00
CPC分类号： H01L23/49816 , H01L21/4853 , H01L23/49838 , H01L23/49822 , H01L24/16 , H01L2224/16227
摘要： In some aspects, the disclosure is directed a module for improving mechanical, electrical, or thermal performance. In some embodiments, the module includes a bottom surface, a side surface, a first solder bump disposed on the bottom surface, and a second solder bump disposed on the bottom surface. In some embodiments, the bottom surface extends in a first lateral direction and a second lateral direction perpendicular to the first lateral direction. In some embodiments, the side surface extends in a vertical direction perpendicular to the first lateral direction and the second lateral direction. In some embodiments, the second solder bump is adjacent to the side surface. In some embodiments, the first solder bump has a first length in the first lateral direction. In some embodiments, the second solder bump has a second length in the first lateral direction. In some embodiments, the first length is greater than the second length.
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公开(公告)号：US12001372B2
公开(公告)日：2024-06-04
申请号：US17694106
申请日：2022-03-14
发明人： Jeffrey Ronald Dorst
CPC分类号： G06F13/4221 , G06F9/30123
摘要： A PCIe retimer includes read-only vendor registers with low latency mode entry and exit values. In-band low latency switching logic monitors the output of an elastic buffer for read commands of the vendor registers and, when such read commands are received, reads the corresponding address and switches a multiplexer between a link training data path and a low latency data path based on the return value of the read operation. Read commands, and therefore control of data path switching, is handled entirely in-band. Return values of the read operations indicate success or failure of mode switching to the root complex.
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公开(公告)号：US11995010B2
公开(公告)日：2024-05-28
申请号：US17232944
申请日：2021-04-16
发明人： Marc Pegolotti , Kenny Wu , Ravi Shenoy , Gregorio Gervasio, Jr. , Lalit Chhabra , Mark Karnowski , James Winston Smart , Vuong Cao Nguyen
IPC分类号： G06F13/28 , G06F12/0806 , G06F12/1009 , G06F13/16
CPC分类号： G06F13/1668 , G06F12/0806 , G06F12/1009 , G06F13/28 , G06F2212/608
摘要： Systems and methods relate to a bus adapter for a storage network. The bus adaptor includes a context memory comprising a first storage for uncacheable exchange resource indicators (XRI) and a second storage for cacheable XRI. The bus adapter also includes a host backing store unit configured to provide access to the different tier memories present locally or externally in the host memory extension using several caching sub-units and with the capability of an optional pinning operation for the cacheable XRI based upon at least one of input/output phase, first in line up to a limit, a region of a virtual context address associated with the cacheable XRI indicators, a protocol associated with the cacheable XRI, a size of a transaction, or work queue information.
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26.发明公开公开(公告)号：US20240170384A1
公开(公告)日：2024-05-23
申请号：US17989559
申请日：2022-11-17
发明人： Li Sun , Chang Kyu Choi , Sarah Haney
IPC分类号： H01L23/498 , H01L23/31 , H01L23/552
CPC分类号： H01L23/49838 , H01L23/3121 , H01L23/49811 , H01L23/49866 , H01L23/552
摘要： DSM-LGA using substrates with different surface finish options include copper posts for electrical communication. The copper posts include a height-to-width ratio that cannot be achieved in traditional copper posts, as well as a taper ratio that forms a more rectangular cross section as opposed to traditional copper posts. Additionally, by using copper, the copper posts include a relatively high thermal conductivity (as compared to solder), thus allowing the copper posts to dissipate thermal energy generated by integrated circuits and other processors. Copper posts can take the form of a single, cylindrical post. Alternatively, copper posts can be merged to form a variety of copper structures used for various applications, including I/O, grounding/isolation, and substrate support.
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公开(公告)号：US20240163919A1
公开(公告)日：2024-05-16
申请号：US18307391
申请日：2023-04-26
IPC分类号： H04W74/08 , H04W72/0453
CPC分类号： H04W74/0808 , H04W72/0453
摘要： A first device includes at least one processor configured to communicate with the second device using a primary channel, detect occupation on the primary channel by a third device, and communicate with the second device using a secondary channel in response to the occupation by the third device. The secondary channel is chosen from a set of channels. The set of channels being determined at least partially in response to information or parameters exchanged during association of the first device and the second device.
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公开(公告)号：US11985389B2
公开(公告)日：2024-05-14
申请号：US17372636
申请日：2021-07-12
发明人： Zhijie Yang , Xuemin Chen
IPC分类号： H04N21/4728 , H04N21/431 , H04N21/472
CPC分类号： H04N21/4728 , H04N21/4316 , H04N21/47217
摘要： Systems, methods and apparatus for processing video can include a processor. The processor can be configured to perform object detection to detect visual indications of potential objects of interest in a video scene, to receive a selection of an object of interest from the potential objects of interest, and to provide enhanced video content within the video scene for the object of interest indicated by the selection.
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29.发明公开公开(公告)号：US20240154591A1
公开(公告)日：2024-05-09
申请号：US18335217
申请日：2023-06-15
发明人： Jiawen Zhang , Delong Cui , Afshin Momtaz , Kun Chuai , Jun Cao
CPC分类号： H03F3/45475 , G01J1/44 , H03G3/30 , H03F2200/372 , H03G2201/103
摘要： An optical module includes an optical receiver with a complementary metal-oxide semiconductor (CMOS) transimpedance amplifier (TIA) and a digital signal processing (DSP) circuit. The DSP circuit is integrated with the CMOS TIA and facilitates adaptability of the CMOS TIA, and the CMOS TIA can adapt by using information provided by the DSP circuit.
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公开(公告)号：US20240146325A1
公开(公告)日：2024-05-02
申请号：US17976129
申请日：2022-10-28
IPC分类号： H03M1/66
CPC分类号： H03M1/662
摘要： Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.
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