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公开(公告)号：US20240314965A1
公开(公告)日：2024-09-19
申请号：US18121269
申请日：2023-03-14
Applicant: Quanta Computer Inc.
Inventor： Chao-Jung CHEN , Chih-Hsiang LEE , Yao-Long LIN , Cheng-Pang KUAN
IPC: H05K7/14
CPC classification number: H05K7/1489
Abstract: An air-shielding mechanism for a computing system is disclosed. A computing system includes a server chassis with a slot configured to receive a computing node. An air-shielding mechanism is positioned within the slot and includes a connecting rod movably coupled within the slot and a movable flap coupled to the connecting rod. The connecting rod rotates in a first direction in response to pressure generated by contact between the computing node inserted within the slot and the connecting rod. The movable flap is in a closed position when the computing node is absent from the slot, and the movable flap is in an open position when the computing node is fully inserted within the respective slot. The movable flap rotates in a second direction while the connecting rod is rotating in the first direction, the second direction being opposite the first direction.
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公开(公告)号：US20240311160A1
公开(公告)日：2024-09-19
申请号：US18184518
申请日：2023-03-15
Applicant: Quanta Computer Inc.
Inventor： Yu-Han LIN
IPC: G06F9/4401
CPC classification number: G06F9/4403
Abstract: An example computer-implemented method is for initializing a compute system. The computer-implemented method includes causing a cache to be initialized in a central processing unit (CPU) of the compute system in response to basic input/output system (BIOS) code being executed directly from flash memory. Moreover, a communication path is initialized, the communication path extending between the CPU and memory corresponding to a baseboard management controller (BMC) of the compute system. BIOS firmware is copied from the BMC memory to the CPU cache, and the BIOS firmware is initiated from the CPU cache. The computer-implemented method includes causing a memory controller of the CPU to be initialized, in addition to causing a portion of the BIOS firmware to be copied from the CPU cache to memory corresponding to the CPU. Furthermore, a portion of the BIOS firmware is initiated from the CPU memory.
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公开(公告)号：US12090100B2
公开(公告)日：2024-09-17
申请号：US17827951
申请日：2022-05-30
Applicant: Quanta Computer Inc.
Inventor： Chia-Yuan Chang , Jung-Wen Chang , Pao-Hsien Chang
Abstract: A telehealth movable vehicle is provided. The telehealth movable vehicle includes a movable part, a fixed member, a slidable member, a bracket, a video/audio transceiver module, and a telescopic rod. The fixed member is affixed to the movable part, and has a guide rail. The slidable member is movably connected to the guide rail. The bracket is affixed to the slidable member. The video/audio transceiver module is disposed on the bracket. The telescopic rod is connected to the fixed member and the slidable member. The telescopic rod is configured to drive the slidable member to move along the guide rail relative to the fixed member.
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公开(公告)号：US20240298953A1
公开(公告)日：2024-09-12
申请号：US18464629
申请日：2023-09-11
Applicant: Quanta Computer Inc.
Inventor： Chia-Yuan CHANG , Jung-Wen CHANG , Chien-Hung LIN
CPC classification number: A61B5/332 , A61B5/26 , A61B5/282 , A61B5/352 , A61B5/355 , A61B5/681 , A61B2562/166
Abstract: An embodiment of the invention provides an electrocardiography (ECG) signal processing device. The ECG signal processing device includes a first part, a second part and a flexible printed circuit board. The first part may comprise a first electrode and a processing circuit. The second part includes a second electrode. The flexible printed circuit board is coupled to the first part and the second part to fold the first part and the second part. When a closed loop is formed between the first electrode and the second electrode, the processing circuit obtains an ECG signal from the user.
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公开(公告)号：US12079062B2
公开(公告)日：2024-09-03
申请号：US18048661
申请日：2022-10-21
Applicant: Quanta Computer Inc.
Inventor： Yung-Fu Li
IPC: G06F1/32 , G06F1/3225 , G06F1/3234 , G06F1/3287 , G06F1/3203
CPC classification number: G06F1/3287 , G06F1/3225 , G06F1/3275 , G06F1/3203
Abstract: A system and method to save power in a computer system is disclosed. The system includes a power controller controlling connection of power to each of a plurality of memory components. A processor is coupled to the memory components. The processor operates with varying utilization levels of the memory components. A management controller is coupled to the processor and the power controller. The management controller determines a period of low utilization based on memory utilization data from the processor. The management controller commands the power controller to disable power to some of the plurality of memory components during the period of low utilization.
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Patent Agency Ranking
公开(公告)号：US20240291225A1
公开(公告)日：2024-08-29
申请号：US18659591
申请日：2024-05-09
Applicant: Quanta Computer Inc.
Inventor： Chang-Sheng LIN , Hsiao-Hsien Weng , Zong-Syun He
CPC classification number: H01S3/1305 , G02B6/4246 , H01S5/0261 , H01S5/0617 , H01S5/06825 , H01S5/0683
Abstract: A system and method for safe use of an optics assembly with an external light source and an optically coupled optics module is disclosed. The system includes an external light module emitting a continuous wave laser through an output port. An optics module has an input port and a memory. The optics module generates a modulated optical signal. The memory stores the power level of the continuous wave laser signal received by the optics module. An optical jumper is provided for coupling the output port with the input port. A communication bus is coupled between a controller and the external light source module. The controller sets the external light source at a low power level and transitions the external light source to a high power level when the stored power level of the continuous wave laser signal received by the optics module exceeds a predetermined level.
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公开(公告)号：US20240260221A1
公开(公告)日：2024-08-01
申请号：US18162882
申请日：2023-02-01
Applicant: Quanta Computer Inc.
Inventor： Yaw-Tzorng TSORNG , Tung-Hsien WU , Chia-Hung KAO , Jun-Zhe WENG
CPC classification number: H05K7/1461 , G06F1/185 , H05K7/1407 , H05K7/1418
Abstract: A riser bracket for a computing device includes a plurality of structural members configured to receive a computing component and an adjustable fixing bracket mechanically coupled to the plurality of structural members. The adjustable fixing bracket has a plurality of configurations that includes a first configuration and a second configuration. The adjustable fixing bracket has a first height in the first configuration that is greater than a second height in the second configuration. The adjustable fixing bracket includes a first slide bracket that is slidably mounted to a support bracket. The support bracket is fixed relative to the first slide bracket and the plurality of structural members. The first slide bracket is slidable along the support bracket to change the adjustable fixing bracket between the first configuration and the second configuration.
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公开(公告)号：US12052846B2
公开(公告)日：2024-07-30
申请号：US17670113
申请日：2022-02-11
Applicant: Quanta Computer Inc.
Inventor： Yi-Chieh Chen , Yueh-Chang Wu , Ching-Yi Shih , Kang Hsu
CPC classification number: H05K7/20409 , F28D21/00 , F28F3/02 , F28F21/084 , H05K7/20518 , H05K7/20727 , B23P2700/10 , F28D2021/0029
Abstract: A heat sink comprises a first portion and a second portion. The first portion is configured to contact a heat-generating electronic component. The first portion is formed from a first group of materials and has a first plurality of fins. The second portion is coupled to the first portion. The second portion is formed from a second group of materials and has a second plurality of fins. The second group of materials is different than the first group of materials. The first group of materials can include extruded aluminum, stamped aluminum, or both. The second group of materials can include die-cast metal. The first plurality of fins can have a smaller fin pitch than the second plurality of fins. The heat sink can further comprise a third portion coupled to the first portion, such that the first portion is positioned between the second portion and the third portion.
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公开(公告)号：US20240242542A1
公开(公告)日：2024-07-18
申请号：US18450611
申请日：2023-08-16
Applicant: Quanta Computer Inc.
Inventor： Ko-Chien CHUANG , Yu-Hsin CHOU , Chih-Yi HUANG , Shao-Fan WANG
Abstract: An embodiment of the invention provides a gesture recognition device. The gesture recognition device may include an image extraction device, a storage circuit and a recognition circuit. The image extraction device may extract a first gesture image. The storage circuit may store a plurality of gesture patterns. The recognition circuit may obtain the first gesture information corresponding to the first gesture image according to the first gesture image, select a gesture pattern corresponding to the first gesture image from the gesture patterns according to the first gesture information, and perform the function that corresponds to the selected gesture pattern.
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公开(公告)号：US20240241189A1
公开(公告)日：2024-07-18
申请号：US18155586
申请日：2023-01-17
Applicant: Quanta Computer Inc.
Inventor： Kuo-Chan HSU , Yun-Teng SHIH , Chia-Wei LEE
IPC: G01R31/40 , G01R31/319 , G01R31/3193
CPC classification number: G01R31/40 , G01R31/31924 , G01R31/31932
Abstract: A test load circuit includes a test load, a current sensor, and comparator. The test load is connected to a voltage source of a power supply. The current sensor is configured to detect the amount of current flowing through the test load. The comparator has a first input connected to a feedback signal having a voltage associated with the test load current, a second input connected to a command signal having has a voltage associated with a target current through the test load, and an output connected to the test load. The output of the comparator has a voltage that is based on the current difference between the target current and the test load current. The test load has a variable resistance that is controllable by the output of the comparator to adjust the test load current and cause the test load current to match the target current.
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