公开(公告)号：US20110145460A1

公开(公告)日：2011-06-16

申请号：US13028416

申请日：2011-02-16

Applicant: Gregory Conti ,  Franck Dahan

Inventor： Gregory Conti ,  Franck Dahan

IPC: G06F13/24

CPC classification number: G06F13/24 ,  Y02D10/14

Abstract: A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.

Abstract translation: 可在各种执行环境中操作的处理系统。 该系统包括具有各自的中断输入的多个处理器核，各自等待中断输出和相应的安全输出。 该系统还包括耦合到至少一个处理器核心的寄存器，用于识别主动执行环境。 该系统还包括全局中断处理器，其可操作以选择性地将中断路由到所述多个处理器核的一个或多个中断输入。 该系统还包括具有多个中断相关输出线的转换电路，并且所述转换电路馈送至少一些所述相应的等待中断输出和相应的安全输出并由所述寄存器馈送。

公开(公告)号：US07882625B2

公开(公告)日：2011-02-08

申请号：US12033128

申请日：2008-02-19

Applicant: Kengo Aoya

Inventor： Kengo Aoya

IPC: H05K3/30

CPC classification number: H05K3/3478 ,  H01L21/4853 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2203/041 ,  H05K2203/0557 ,  Y10T29/41 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/5313 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The objective of this invention is to provide a transfer mask that is able to accurately pass micro-balls onto terminal areas on a substrate. A thin plate transfer mask 200 is arranged facing a substrate 100, and possesses a plurality of through-holes 242 for the purpose of passing micro-balls (solder balls) onto a plurality of terminal areas 108 formed on one surface of a substrate 100. Slits 230, 232, 234, 236 formed in the surface of the transfer mask 200 extending in the length direction and the width direction of the transfer mask 200, inside the substrate edge P1 and outside the area in which the plurality of through-holes 242 is formed when it is facing the substrate 100.

Abstract translation: 本发明的目的是提供一种能够将微球精确地传递到基底上的终端区域的转印掩模。 薄板转印掩模200面向衬底100布置，并且具有多个通孔242，用于将微球（焊球）传递到形成在衬底100的一个表面上的多个端子区域108上。 在转印掩模200的表面上形成的狭缝230,232,234,236，其在基板边缘P1的内部和在多个通孔242的区域的外部沿着传送掩模200的长度方向和宽度方向延伸 当其面向基板100时形成。

公开(公告)号：US07279920B2

公开(公告)日：2007-10-09

申请号：US11100040

申请日：2005-04-06

Applicant: Bradley Allen Kramer

Inventor： Bradley Allen Kramer

IPC: G01R31/26

CPC classification number: G01R31/2822 ,  G01R31/3025 ,  G01R31/311

Abstract: System and method for integrated circuit manufacturing. A preferred embodiment comprises transmitting a first set of data to integrated circuits (ICs) while they are in an on-wafer state and having each IC store the first set of data into memory, transmitting a second set of data to the ICs and having the ICs compare the second set of data with the first set of data stored in the memory, reading out the results of the comparisons, and marking an IC as being defective if the comparison indicates that that the first set of data did not match the second set of data. Each IC features an antenna formed in the scribe line region adjacent to the IC so that communications can take place while the IC remains on the wafer without the need to use electrical probes.

Abstract translation: 集成电路制造的系统和方法。 优选实施例包括当第一组数据处于晶片状态并且每个IC将第一组数据存储到存储器中时将第一组数据传输到集成电路（IC），将第二组数据发送到IC并具有 IC将第二组数据与存储在存储器中的第一组数据进行比较，读出比较结果，并且如果比较指示第一组数据与第二组不匹配，则将IC标记为有缺陷 数据的。 每个IC具有形成在与IC相邻的划片线区域中的天线，使得当IC保留在晶片上时可以进行通信，而不需要使用电探针。

公开(公告)号：USRE36522E

公开(公告)日：2000-01-18

申请号：US177447

申请日：1998-09-30

Applicant: Steven J. Wallace ,  LaVaughn F. Watts, Jr.

Inventor： Steven J. Wallace ,  LaVaughn F. Watts, Jr.

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F13/4234 ,  G06F13/385

Abstract: A method of dynamically interfacing an application processor with a plurality of peripheral ports is shown, including the use of an expanded memory interface for controlling a plurality of memory components for an application processor external to the interface. The application processor is connected to the expanded memory interface, which is in turn coupled to at least one status port to facilitate communication between the application processor and the status port.

Abstract translation: 示出了将应用处理器与多个外围端口动态接口的方法，包括使用扩展存储器接口来控制用于接口外部的应用处理器的多个存储器组件。 应用处理器连接到扩展存储器接口，扩展存储器接口又耦合到至少一个状态端口，以便于应用处理器和状态端口之间的通信。

公开(公告)号：US5925927A

公开(公告)日：1999-07-20

申请号：US991725

申请日：1997-12-16

Applicant: John Orcutt

Inventor： John Orcutt

IPC: H01L23/495 ,  H05K3/34 ,  H01L23/52 ,  H01L23/48 ,  H01L23/50

CPC classification number: H05K3/3426 ,  H01L23/49548 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/181 ,  Y02P70/613

Abstract: A lead frame, method of making same and semiconductor package containing the lead frame. The semiconductor package includes the lead frame which includes an essentially flat, planar lead frame body and lead frame leads extending from the lead frame body, the lead frame leads extending partially out of the plane of the lead frame body. A semiconductor chip is disposed on the lead frame and an encapsulant encapsulates the lead frame body, the semiconductor chip and a portion of the lead frame leads, with a portion of the lead frame leads extending external to the encapsulant. The two dimensional cross section can be essentially in the shape of a "U", essentially sinusoidal in shape, the sinusoidal shape having an odd number of half cycles of the sinusoidal shape or essentially in the shape of a "W".

Abstract translation: 引线框架，其制造方法以及包含引线框架的半导体封装。 半导体封装包括引线框架，该引线框架包括基本上平坦的平面引线框架体和从引线框架主体延伸的引线框架引线，引线框架引线部分地延伸出引线框架主体的平面。 半导体芯片设置在引线框架上，并且密封剂封装引线框体，半导体芯片和引线框架的一部分引线，引线框架引线的一部分在密封剂外部延伸。 二维截面基本上可以是基本上为正弦形状的“U”形状，正弦形状具有奇数个正弦形状的半个周期或基本上呈“W”形的形状。

公开(公告)号：US5917839A

公开(公告)日：1999-06-29

申请号：US863851

申请日：1997-05-27

Applicant: Masashi Hashimoto ,  Anjana Ghosh

Inventor： Masashi Hashimoto ,  Anjana Ghosh

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/00

CPC classification number: G06F11/1056 ,  H03M13/098

Abstract: In a dynamic random access memory unit 10, a circuit, 61.sub.0 -61.sub.N.sbsb.--.sub.1, 615, and 617, is provided in which a non-change of each address signal of an address signal group during a next consecutive clock cycle blocks the application of the read activation control signal to the memory unit 10. In this manner, the memory unit 10 is inactive (i.e., does not perform a read operation) during the modify portion of a read-modify-write operation so that potential conflicts in the operation of the memory unit 10 are avoided.

Abstract translation: 在动态随机存取存储器单元10中，提供电路610-61N-1,615和617，其中在下一个连续时钟周期期间地址信号组的每个地址信号的不变化阻止了 读取激活控制信号发送到存储器单元10.以这种方式，在读取 - 修改 - 写入操作的修改部分期间，存储器单元10不活动（即，不执行读取操作），使得操作中的潜在冲突 避免了存储器单元10。

公开(公告)号：US5528503A

公开(公告)日：1996-06-18

申请号：US56007

申请日：1993-04-30

Applicant: Stephen F. Moore ,  Thomas E. Byrd

Inventor： Stephen F. Moore ,  Thomas E. Byrd

IPC: G06F15/00 ,  G05B19/418 ,  G06F9/46 ,  G06F19/00

CPC classification number: G05B19/41865 ,  G05B19/4188 ,  Y02P90/18 ,  Y02P90/20 ,  Y02P90/24

Abstract: An integrated automation development system (10) for controlling and coordinating manufacturing equipment (24) employs a plurality of server processes (14, 16, 22, 28, 34, 36). Each server process includes a messaging manager (45) for receiving ASCII messages, and an interpreter (43) for evaluating the received ASCII messages and identifying commands within the messages. The server process further includes a command manager (41) for receiving and executing the commands, and a logic controller (47) for managing the logic flow of the command execution by the command manager (41). The servers may include additional commands (48) that enable them to serve as queue servers (34), terminal servers (28), and other application-specific server processes.

Abstract translation: 用于控制和协调制造设备（24）的综合自动化开发系统（10）采用多个服务器进程（14,16,22,28,34,36）。 每个服务器进程包括用于接收ASCII消息的消息管理器（45）和用于评估所接收的ASCII消息并在消息内识别命令的解释器（43）。 服务器进程还包括用于接收和执行命令的命令管理器（41），以及用于管理由命令管理器（41）执行命令的逻辑流的逻辑控制器（47）。 服务器可以包括使其能够用作队列服务器（34），终端服务器（28）和其他应用特定服务器进程的附加命令（48）。

公开(公告)号：US09222969B2

公开(公告)日：2015-12-29

申请号：US13602741

申请日：2012-09-04

Applicant: Jin Liu

Inventor： Jin Liu

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2884 ,  G01R31/024

Abstract: Assessing open circuit and short circuit defect levels in circuits implemented in state of the art ICs is difficult when using conventional test circuits, which are designed to assess continuity and isolation performance of simple structures based on individual design rules. Including circuit blocks from ICs in test circuits provides a more accurate assessment of defect levels expected in ICs using the circuit blocks. Open circuit defect levels may be assessed using continuity chains formed by serially linking continuity paths in the circuit blocks. Short circuit defect levels may be assessed by using parallel isolation test structures formed by linking isolated conductive elements in parallel to buses. Forming isolation connections on a high metal level enables location of shorted elements using voltage contrast on partially deprocessed or partially fabricated test circuits.

Abstract translation: 在使用传统测试电路时，评估现有IC中实现的电路中的开路和短路缺陷电平是困难的，这些常规测试电路被设计为基于各个设计规则来评估简单结构的连续性和隔离性能。 在测试电路中包括来自IC的电路块可以更准确地评估使用电路块的IC中预期的缺陷水平。 可以使用通过串联链接电路块中的连续性路径形成的连续性链来评估开路缺陷水平。 可以通过使用与母线平行连接隔离导电元件形成的并联隔离测试结构来评估短路缺陷水平。 在高金属层上形成隔离连接可以使用部分去处理或部分制造的测试电路上的电压对比来定位短路元件。

公开(公告)号：US08755877B2

公开(公告)日：2014-06-17

申请号：US13434725

申请日：2012-03-29

Applicant: Vasile Zoica

Inventor： Vasile Zoica

IPC: A61B5/0456

CPC classification number: A61B5/6898 ,  A61B5/0006 ,  A61B5/0022 ,  A61B5/02405 ,  A61B5/04085 ,  A61B5/0452 ,  A61B5/0456 ,  A61B5/6805 ,  A61B5/7203 ,  A61B5/725 ,  A61B5/743 ,  A61B5/746

Abstract: A mobile system for analyzing ECG data includes an analog front end module coupled to a mobile consumer device. The analog front end module is configured to collect ECG data from one or more leads and is operable to convert the analog ECG data to digital ECG data. The mobile consumer device is coupled to receive the digital ECG data, and is configured to perform QRS detection using a filter whose cutoff frequency is adapted to noise level in real time. The ECG signal is amplified non-linearly and three windowed threshold signals (D, E, J) are derived. The cutoff frequency for the QRS detection is dynamically selected as a function of the threshold signals. A sample in the amplified signal is identified to be a heart beat point only when the sample value is equal to the first threshold signal and greater than the filtered threshold signal.

Abstract translation: 用于分析ECG数据的移动系统包括耦合到移动消费者设备的模拟前端模块。 模拟前端模块被配置为从一个或多个引线收集ECG数据，并且可操作以将模拟ECG数据转换为数字ECG数据。 移动消费者设备被耦合以接收数字ECG数据，并且被配置为使用截止频率实时地适应于噪声电平的滤波器来执行QRS检测。 ECG信号被非线性放大，导出三个窗口阈值信号（D，E，J）。 动态地选择QRS检测的截止频率作为阈值信号的函数。 仅当采样值等于第一阈值信号并且大于滤波后的阈值信号时，放大信号中的采样被识别为心跳点。

公开(公告)号：US20110173363A1

公开(公告)日：2011-07-14

申请号：US13028459

申请日：2011-02-16

Applicant: Gregory Conti ,  Franck Dahan

Inventor： Gregory Conti ,  Franck Dahan

IPC: G06F13/24

CPC classification number: G06F13/24 ,  Y02D10/14

Abstract: A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.

Abstract translation: 具有应用程序和维护功能的处理器系统，如果同时执行则会干扰应用程序。 处理器系统包括可在不同安全性和上下文相关模式下操作的一组处理器核心，所述处理器具有至少一个中断输入和至少一个等待中断输出。 所述处理器系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器核中的至少一个可响应于所述中断信号而可操作以调度在时间上分离的维护功能 执行应用程序。