公开(公告)号：US5248628A

公开(公告)日：1993-09-28

申请号：US896537

申请日：1992-06-09

申请人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

发明人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

摘要翻译： 一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔， 在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料 从而可以使存储器件的尺寸小并且可以提高可靠性。 此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。 利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

公开(公告)号：US5043298A

公开(公告)日：1991-08-27

申请号：US619666

申请日：1990-11-28

申请人： Takashi Yamada ,  Fumio Horiguchi ,  Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi

发明人： Takashi Yamada ,  Fumio Horiguchi ,  Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi

IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/417

CPC分类号： H01L27/10808

摘要： When a semiconductor device having a multi-layered contact is fabaricated, the gate electrode is covered with a thick insulator film. A polycrystalline silicon film is formed in a state in which at least the gate electrode in the contact forming area is covered with a first oxidization-proof insulator film. An inter-layer insulator film is then formed in a state in which at least part of the polycrystalline silicon film is covered with a second oxidization-proof insulator film. A first contact hole is formed using the polycrystalline silicon film as an etching stopper, and the polycrystalline silicon film is then oxidized. Furthermore, a second contact hole is formed in the inter-layer insulator film on the upper surface of the second oxidization-proof insulator film using as the etching stopper the polycrystalline silicon film underlying the second oxidization-proof insulator film. Since the polycrystalline silicon film is formed under the inter-layer insulator film in the second contact forming area so as to cover the gate electrode, it acts as a stopper when the second contact is formed to thereby prevent a short circuit with the gate electrode even if there is no distance between the gate electrode and the second contact.

摘要翻译： 当具有多层接触的半导体器件被制造时，栅电极被厚绝缘膜覆盖。 在至少形成接触形成区域中的栅电极被第一耐氧化绝缘膜覆盖的状态下形成多晶硅膜。 然后在至少部分多晶硅膜被第二防氧化绝缘膜覆盖的状态下形成层间绝缘膜。 使用多晶硅膜作为蚀刻阻挡层形成第一接触孔，然后将多晶硅膜氧化。 此外，在第二耐氧化绝缘膜的上表面上的层间绝缘膜中形成第二接触孔，使用作为蚀刻停止层的第二耐氧化绝缘膜的下面的多晶硅膜。 由于在第二接触形成区域中的层间绝缘体膜下方形成多晶硅膜以覆盖栅电极，所以当形成第二接触时，其作为阻挡体，从而防止栅电极的短路甚至 如果栅电极和第二触点之间没有距离。

公开(公告)号：US09064735B2

公开(公告)日：2015-06-23

申请号：US13198359

申请日：2011-08-04

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L27/115 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  G11C16/04

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that has a new structure is provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device has a plurality of memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 非易失性半导体存储器件具有串联连接有多个电可编程存储单元的多个存储器串。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US08551838B2

公开(公告)日：2013-10-08

申请号：US13064559

申请日：2011-03-31

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US08237211B2

公开(公告)日：2012-08-07

申请号：US12556242

申请日：2009-09-09

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/788

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.

摘要翻译： 非易失性半导体存储装置具有串联连接的多个电可重写存储单元的存储串。 非挥发性半导体存储装置还具有形成为相对于基板向上突出的突出层。 存储器串包括：层叠在基板上的多个第一导电层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷存储层，并且能够存储电荷。 多个第一导电层中的每一个包括：平行于基板延伸的底部; 以及沿底部的突出层相对于基板向上延伸的侧部。 该突出层在平行于基板的第一方向上的宽度小于或等于其在层叠方向上的长度。

公开(公告)号：US20110287597A1

公开(公告)日：2011-11-24

申请号：US13064559

申请日：2011-03-31

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/788

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US07977738B2

公开(公告)日：2011-07-12

申请号：US12497010

申请日：2009-07-02

申请人： Yoshihiro Minami ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Yoshihiro Minami ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L27/1022 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

摘要翻译： 半导体存储器件包括电漂浮体; 来源 下水道 栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括具有与排水管相同的导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

公开(公告)号：US07920412B2

公开(公告)日：2011-04-05

申请号：US12605072

申请日：2009-10-23

申请人： Keiji Hosotani ,  Yoshiaki Asao ,  Akihiro Nitayama

发明人： Keiji Hosotani ,  Yoshiaki Asao ,  Akihiro Nitayama

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.

摘要翻译： 磁性随机存取存储器包括第一布线，形成在第一布线上方并与第一布线间隔开的第二布线;形成在与第一布线的上表面接触形成的第一布线和第二布线之间的磁阻效应元件，以及 具有形成在固定层和记录层之间的固定层，记录层和非磁性层，形成在磁阻效应元件上并与磁阻效应元件集成以形成堆叠层的金属层，形成第一侧绝缘膜 在金属层的侧表面，磁阻效应元件和第一布线，与第一侧绝缘膜的侧表面接触形成的第一触点和形成在金属层上的第三布线和第一触点电连接 连接磁阻效应元件和第一触点。

公开(公告)号：US20100172189A1

公开(公告)日：2010-07-08

申请号：US12620986

申请日：2009-11-18

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

IPC分类号： G11C16/04 ,  G11C7/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

摘要翻译： 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US20070187801A1

公开(公告)日：2007-08-16

申请号：US11397726

申请日：2006-04-05

申请人： Yoshiaki Asao ,  Akihiro Nitayama

发明人： Yoshiaki Asao ,  Akihiro Nitayama

IPC分类号： H01L29/12 ,  H01L31/117

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286

摘要： A semiconductor device comprising a semiconductor substrate, a switching element which is provided on the semiconductor substrate, a first interconnect layer which is provided above the semiconductor substrate, a plurality of phase-change memory devices which have phase-change material whose resistance changes by a phase-change due to a temperature change, being stacked, and being connected in series to the first interconnect layer and the switching element, a plurality of first heating elements which are connected in series to the respective phase-change memory devices, and a plurality of second heating elements which are connected to second interconnect layers different from the first interconnect layer, and which are provided so as to correspond to the respective phase-change memory devices.

摘要翻译： 一种半导体器件，包括半导体衬底，设置在所述半导体衬底上的开关元件，设置在所述半导体衬底上方的第一互连层，具有相变材料的多个相变存储器件，所述相变材料的电阻改变为 由于温度变化引起的相变，被堆叠并串联连接到第一互连层和开关元件，多个第一加热元件串联连接到各个相变存储器件，以及多个 第二加热元件连接到与第一互连层不同的第二互连层，并且被设置为对应于各个相变存储器件。