公开(公告)号：US5043298A

公开(公告)日：1991-08-27

申请号：US619666

申请日：1990-11-28

申请人： Takashi Yamada ,  Fumio Horiguchi ,  Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi

发明人： Takashi Yamada ,  Fumio Horiguchi ,  Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi

IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/417

CPC分类号： H01L27/10808

摘要： When a semiconductor device having a multi-layered contact is fabaricated, the gate electrode is covered with a thick insulator film. A polycrystalline silicon film is formed in a state in which at least the gate electrode in the contact forming area is covered with a first oxidization-proof insulator film. An inter-layer insulator film is then formed in a state in which at least part of the polycrystalline silicon film is covered with a second oxidization-proof insulator film. A first contact hole is formed using the polycrystalline silicon film as an etching stopper, and the polycrystalline silicon film is then oxidized. Furthermore, a second contact hole is formed in the inter-layer insulator film on the upper surface of the second oxidization-proof insulator film using as the etching stopper the polycrystalline silicon film underlying the second oxidization-proof insulator film. Since the polycrystalline silicon film is formed under the inter-layer insulator film in the second contact forming area so as to cover the gate electrode, it acts as a stopper when the second contact is formed to thereby prevent a short circuit with the gate electrode even if there is no distance between the gate electrode and the second contact.

摘要翻译： 当具有多层接触的半导体器件被制造时，栅电极被厚绝缘膜覆盖。 在至少形成接触形成区域中的栅电极被第一耐氧化绝缘膜覆盖的状态下形成多晶硅膜。 然后在至少部分多晶硅膜被第二防氧化绝缘膜覆盖的状态下形成层间绝缘膜。 使用多晶硅膜作为蚀刻阻挡层形成第一接触孔，然后将多晶硅膜氧化。 此外，在第二耐氧化绝缘膜的上表面上的层间绝缘膜中形成第二接触孔，使用作为蚀刻停止层的第二耐氧化绝缘膜的下面的多晶硅膜。 由于在第二接触形成区域中的层间绝缘体膜下方形成多晶硅膜以覆盖栅电极，所以当形成第二接触时，其作为阻挡体，从而防止栅电极的短路甚至 如果栅电极和第二触点之间没有距离。

公开(公告)号：US5049957A

公开(公告)日：1991-09-17

申请号：US528086

申请日：1990-05-24

申请人： Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Fumio Horiguchi

发明人： Satoshi Inoue ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Fumio Horiguchi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： In a semiconductor memory device, a storage node electrode having a cavity is provided such that the inner surface of a storage node electrode is used as a capacitor electrode. In a DRAM fabricating method, a storage node electrode having a cavity is formed by laminating a first conductor layer, an insulating film and a second conductor layer, which in turn are patterned into a desired shape, depositing a third conductor layer on the three-layer pattern, performing anisotropic etching so as to cause the third conductor layer to remain only on the side walls of the pattern to thereby form a box-shaped conductor, forming an opening in a part of the box-shaped conductor, removing the insulating film by an etching to thereby form a cavity.

摘要翻译： 在半导体存储器件中，具有空腔的存储节点电极被设置为使得存储节点电极的内表面用作电容器电极。 在DRAM制造方法中，通过层叠第一导体层，绝缘膜和第二导体层来形成具有空腔的存储节点电极，第一导体层，绝缘膜和第二导体层又被图案化成所需形状， 层状图案，进行各向异性蚀刻，以使第三导体层仅保留在图案的侧壁上，从而形成盒状导体，在盒状导体的一部分中形成开口，去除绝缘膜 通过蚀刻从而形成空腔。

公开(公告)号：US5248628A

公开(公告)日：1993-09-28

申请号：US896537

申请日：1992-06-09

申请人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

发明人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

摘要翻译： 一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔， 在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料 从而可以使存储器件的尺寸小并且可以提高可靠性。 此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。 利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

公开(公告)号：US5144579A

公开(公告)日：1992-09-01

申请号：US578608

申请日：1990-09-07

申请人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

发明人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

摘要翻译： 一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔， 在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料 从而可以使存储器件的尺寸小并且可以提高可靠性。 此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。 利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

公开(公告)号：US09580791B2

公开(公告)日：2017-02-28

申请号：US13697164

申请日：2011-04-26

申请人： Satoshi Inoue ,  Shinichi Kawato ,  Nobuhiro Hayashi ,  Tohru Sonoda

发明人： Satoshi Inoue ,  Shinichi Kawato ,  Nobuhiro Hayashi ,  Tohru Sonoda

IPC分类号： C23C16/04 ,  H05B33/10 ,  C23C14/04 ,  B05C21/00 ,  H01L51/00 ,  H01L51/50

CPC分类号： C23C14/042 ,  B05C21/005 ,  H01L51/0011 ,  H01L51/50

摘要： A vapor deposition mask (70) includes a first layer (71), a second layer (72) and a third layer (73) in this order. A plurality of first openings (71h), a plurality of second openings (72h) and a plurality of third openings (73h) are formed respectively in the first layer, the second layer and the third layer. The first openings, the second openings and the third openings communicate with each other, thereby constituting mask openings (75). The opening dimension of the second openings is larger than the opening dimension of the first openings and is larger than the opening dimension of the third openings. With this configuration, it is possible to prevent reduction of the opening dimension of the mask openings or clogging of the mask openings due to the vapor deposition particles adhering to the mask openings.

摘要翻译： 蒸镀掩模（70）依次包括第一层（71），第二层（72）和第三层（73）。 多个第一开口（71h），多个第二开口（72h）和多个第三开口（73h）分别形成在第一层，第二层和第三层中。 第一开口，第二开口和第三开口彼此连通，从而构成掩模开口（75）。 第二开口的开口尺寸大于第一开口的开口尺寸，并且大于第三开口的开口尺寸。 利用这种构造，可以防止由于气相沉积颗粒粘附到掩模开口而导致的掩模开口的开口尺寸的减小或掩模开口的堵塞。

公开(公告)号：US09391275B2

公开(公告)日：2016-07-12

申请号：US13703873

申请日：2011-08-17

申请人： Tohru Sonoda ,  Nobuhiro Hayashi ,  Shinichi Kawato ,  Satoshi Inoue

发明人： Tohru Sonoda ,  Nobuhiro Hayashi ,  Shinichi Kawato ,  Satoshi Inoue

IPC分类号： C23C16/00 ,  H01L51/00 ,  C23C14/04 ,  H01L27/32 ,  H01L51/56

CPC分类号： H01L51/0008 ,  C23C14/042 ,  H01L27/3211 ,  H01L27/3244 ,  H01L51/0011 ,  H01L51/56

摘要： A vapor deposition source (60), a plurality of control plates (80) and a vapor deposition mask (70) are disposed in this order. A substrate (10) is moved relative to the vapor deposition mask in a state in which the substrate and the vapor deposition mask are spaced apart at a fixed interval. Vapor deposition particles (91) discharged from a vapor deposition source opening (61) of the vapor deposition source pass through neighboring inter-control plate spaces (81) and mask openings (71) formed in the vapor deposition mask, and then adhere to the substrate to form a coating film (90). At least a part of the coating film is formed by the vapor deposition particles that have passed through two or more different inter-control plate spaces. It is thereby possible to form a coating film in which edge blur and variations in the thickness are suppressed.

摘要翻译： 蒸镀源（60），多个控制板（80）和蒸镀掩模（70）依次配置。 在基板和气相沉积掩模以固定间隔间隔开的状态下，基板（10）相对于气相沉积掩模移动。 从气相沉积源的气相沉积源开口（61）排出的气相沉积颗粒（91）通过相邻的控制板间隙（81）和形成在气相沉积掩模中的掩模开口（71），然后粘附到 基板以形成涂膜（90）。 涂膜的至少一部分由已经通过两个或更多个不同的控制间隙的气相沉积颗粒形成。 由此，可以形成抑制边缘模糊和厚度变化的涂膜。

公开(公告)号：US08845808B2

公开(公告)日：2014-09-30

申请号：US13997173

申请日：2011-12-19

申请人： Tohru Sonoda ,  Shinichi Kawato ,  Satoshi Inoue ,  Satoshi Hashimoto

发明人： Tohru Sonoda ,  Shinichi Kawato ,  Satoshi Inoue ,  Satoshi Hashimoto

IPC分类号： C23C14/26 ,  C23C16/448 ,  H05B33/10 ,  C23C14/24 ,  H01L21/02 ,  H01L51/00 ,  H01L51/56

CPC分类号： C23C16/45578 ,  C23C14/24 ,  C23C14/243 ,  H01L21/02263 ,  H01L51/001 ,  H01L51/56 ,  H05B33/10

摘要： A vapor deposition device (50) in accordance with the present invention is a vapor deposition device for forming a film on a film formation substrate (60), the vapor deposition device including a vapor deposition source (80) that has an injection hole (81) from which vapor deposition particles are injected, a vapor deposition particle crucible (82) for supplying the vapor deposition particles to the vapor deposition source (80), and a rotation motor (86) for changing a distribution of the injection amount of the vapor deposition particles by rotating the vapor deposition source (80).

摘要翻译： 根据本发明的蒸镀装置（50）是在成膜基板（60）上形成膜的蒸镀装置，其特征在于，所述蒸镀装置具有：蒸镀源（80），具有喷射孔 ），用于将气相沉积粒子供给到气相沉积源（80）的气相沉积粒子坩埚（82）和用于改变蒸汽喷射量分布的旋转马达（86） 通过旋转气相沉积源（80）来沉积颗粒。

公开(公告)号：US08673082B2

公开(公告)日：2014-03-18

申请号：US13980875

申请日：2012-01-13

申请人： Satoshi Inoue ,  Shinichi Kawato ,  Tohru Sonoda

发明人： Satoshi Inoue ,  Shinichi Kawato ,  Tohru Sonoda

IPC分类号： C23C16/00

CPC分类号： C23C16/448 ,  C23C14/243 ,  C23C16/042 ,  G03B37/06 ,  H01L51/0008

摘要： A crucible (50) of the present invention includes: an opening (55a) from which vapor deposition particles are injected toward a film formation substrate on which a film is to be formed; a focal point member (54a), provided so as to face the opening (55a), which reflects vapor deposition particles injected from the opening (55a); and a revolution paraboloid (55b) which reflects, toward the film formation substrate, vapor deposition particles which have been reflected by the focal point member (54a).

摘要翻译： 本发明的坩埚（50）包括：朝向要在其上形成膜的成膜基板上注入蒸镀颗粒的开口（55a） 设置成面对开口（55a）的焦点部件（54a），其反射从开口（55a）喷射的气相沉积粒子; 以及向所述成膜基板反射已被所述焦点部件（54a）反射的气相沉积粒子的旋转抛物面（55b）。

公开(公告)号：US20140014036A1

公开(公告)日：2014-01-16

申请号：US14007956

申请日：2012-03-23

申请人： Tohru Sonoda ,  Shinichi Kawato ,  Satoshi Inoue ,  Satoshi Hashimoto

发明人： Tohru Sonoda ,  Shinichi Kawato ,  Satoshi Inoue ,  Satoshi Hashimoto

IPC分类号： H01L21/02 ,  B65D85/00

摘要： A vapor deposition particle emitting device of the present invention includes: a nozzle section (110) having emission holes (111) from which gaseous vapor deposition particles are emitted out; a heating plate unit (100), provided in the nozzle section (110), which is made up of heating plates (101) each having a surface on which a vapor deposition material remains as a result of adherence of vapor deposition particles to the surface; and a heating device (160) for heating the vapor deposition material, which is thus remaining on the surface of each of the heating plates (101), so that a temperature of the vapor deposition material is not less than a temperature at which to become transformed into gaseous form.

摘要翻译： 本发明的气相沉积粒子发射装置包括：喷嘴部分（110），其具有从其中排出气态气相沉积颗粒的发射孔（111）; 设置在所述喷嘴部分（110）中的加热板单元（100），所述加热板单元由加热板（101）组成，所述加热板具有由于气相沉积颗粒粘附到所述表面而具有气相沉积材料的表面的表面 ; 以及用于加热蒸镀材料的加热装置（160），其被保持在每个加热板（101）的表面上，使得蒸镀材料的温度不低于成为 转化成气态。

公开(公告)号：US08628620B2

公开(公告)日：2014-01-14

申请号：US13977645

申请日：2011-12-28

申请人： Shinichi Kawato ,  Nobuhiro Hayashi ,  Tohru Sonoda ,  Satoshi Inoue

发明人： Shinichi Kawato ,  Nobuhiro Hayashi ,  Tohru Sonoda ,  Satoshi Inoue

IPC分类号： C23C16/04 ,  C23C16/00 ,  C23C14/24 ,  C23C14/22 ,  C23C14/00

CPC分类号： H01L21/02263 ,  C23C14/042 ,  C23C14/12 ,  C23C14/562 ,  H01L21/67017 ,  H01L51/0008 ,  H01L51/56

摘要： A vapor deposition device (50) includes a mask (60) having periodic patterns, and only a region of the mask (60) where a one-period pattern is formed is exposed. A length of the mask base material along a direction perpendicular to a long-side direction of the mask base material is shorter than a length of a film formation substrate (200) along a direction of scanning of the film formation substrate (200). The mask (60) is provided so that the long-side direction of the mask base material is perpendicular to the direction of scanning and that the exposed region is allowed to move in a direction perpendicular to the direction of scanning by rotation of a wind-off roll (91) and a wind-up roll (92).

摘要翻译： 气相沉积装置（50）包括具有周期性图案的掩模（60），并且仅露出形成有一个周期图案的掩模（60）的区域。 掩模基材沿着与掩模基材的长边方向垂直的方向的长度比成膜基板（200）沿着成膜基板（200）的扫描方向的长度短。 掩模（60）设置成使得掩模基材的长边方向垂直于扫描方向，并且允许暴露区域沿着与扫描方向垂直的方向移动， 卷筒（91）和卷绕辊（92）。