公开(公告)号：US12211586B2

公开(公告)日：2025-01-28

申请号：US18476030

申请日：2023-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY LIMITED ,  TSMC CHINA COMPANY LIMITED

Inventor： Xiu-Li Yang ,  He-Zhou Wan ,  Mu-Yang Ye ,  Lu-Ping Kong ,  Ming-Hung Chang

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22

Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

公开(公告)号：US12176062B2

公开(公告)日：2024-12-24

申请号：US18336428

申请日：2023-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC Nanjing Company Limited ,  TSMC China Company Limited

Inventor： He-Zhou Wan ,  Xiu-Li Yang ,  Pei-Le Li ,  Ching-Wei Wu

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/12 ,  G11C8/10

Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

公开(公告)号：US20240071470A1

公开(公告)日：2024-02-29

申请号：US18499449

申请日：2023-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC Nanjing Company Limited ,  TSMC China Company Limited

Inventor： He-Zhou WAN ,  Xiu-Li YANG ,  Mu-Yang YE ,  Yan-Bo SONG

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4085 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4094

Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

公开(公告)号：US11876088B2

公开(公告)日：2024-01-16

申请号：US17527883

申请日：2021-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

Inventor： Yang Zhou ,  Liu Han ,  Qingchao Meng ,  XinYong Wang ,  ZeJian Cai

IPC: H01L27/02 ,  H01L27/092 ,  H01L25/065 ,  H01L23/48 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8238 ,  H01L25/00 ,  G06F30/392 ,  H01L21/74

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76898 ,  H01L21/823892 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0928 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.

公开(公告)号：US20230402446A1

公开(公告)日：2023-12-14

申请号：US18447857

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED ,  TSMC CHINA COMPANY, LIMITED

Inventor： Liu HAN ,  Xin Yong WANG ,  Qingchao MENG ,  Huaixin XIAN ,  Jing DING

IPC: H01L27/02 ,  H03K19/00 ,  H01L27/06

CPC classification number: H01L27/0207 ,  H03K19/0016 ,  H01L27/0629

Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.

公开(公告)号：US11705175B2

公开(公告)日：2023-07-18

申请号：US17883364

申请日：2022-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

Inventor： XiuLi Yang ,  Ching-Wei Wu ,  He-Zhou Wan ,  Kuan Cheng ,  Luping Kong

IPC: G11C8/18 ,  G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C8/18 ,  G11C7/106 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

Abstract: A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

公开(公告)号：US20230049698A1

公开(公告)日：2023-02-16

申请号：US17973823

申请日：2022-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC Nanjing Company Limited ,  TSMC China Company Limited

Inventor： He-Zhou WAN ,  Xiu-Li YANG ,  Mu-Yang YE ,  Yan-Bo SONG

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094

Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

公开(公告)号：US20220375512A1

公开(公告)日：2022-11-24

申请号：US17883364

申请日：2022-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

Inventor： XiuLi YANG ,  Ching-Wei WU ,  He-Zhou WAN ,  Kuan CHENG ,  Luping KONG

IPC: G11C11/418

Abstract: A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

公开(公告)号：US11507068B2

公开(公告)日：2022-11-22

申请号：US16490407

申请日：2017-03-01

Applicant: JOINT-STOCK COMPANY ASE ENGINEERING COMPANY ,  JOINT STOCK COMPANY “SCIENCE AND INNOVATIONS”

Inventor： Vyacheslav Vladimirovich Alenkov ,  Serguey Viktorovich Yergopulo ,  Yevgeny Mikhaylovich Chebotarev ,  Filipp Mikhailovich Novodvorsky

IPC: G05B19/418 ,  G06F16/93 ,  G06F16/9032

Abstract: A method for managing a life cycle of a complex engineering facility, comprising several steps. The steps include forming a facility structure of the facility; selecting constituent elements of the facility structure and the relationships between the constituent elements and a location of each of the constituent elements in a decomposition structure of the facility; forming a linked array of requirements related to the facility and to processes of implementation of the requirement for the facility; planning and accounting for the requirements in accordance with the structural decomposition of the facility, the requirements being assigned a certain status; and forming databases intended for storing an associated array of information about the constituent elements of the facility, the associated array of information comprising at least a plurality of documents related to design data and/or to supply and procurement data and/or to pre-commissioning data and/or operation data and/or facility configuration data.

公开(公告)号：US20210098141A1

公开(公告)日：2021-04-01

申请号：US16981657

申请日：2017-12-29

Applicant: JOINT STOCK COMPANY ENGINEERING COMPANY ASE ,  JOINT STOCK COMPANY ATOMENERGOPROEKT

Inventor： Sergey Viktorovich KOROVKIN ,  Evgeniya Viktorovna TUTUNINA

IPC: G21C15/25 ,  G21C15/18

Abstract: A single-loop nuclear power plant with a pressurized coolant, comprising a power generating unit and a throttling device having an impeller, which are interconnected by an outlet pipe and a feed pipe, and a steam turbine connected to the throttling device and to a condenser connected to the throttling device, which device is a throttling steam generator vertically divided into a vapour zone, a high pressure zone, and a low pressure zone by horizontal sealed partitions. The high pressure zone is connected to the the feed pipe and is connected to the low pressure zone by throttling nozzles provided in the partition between said zones, and the low pressure zone is connected to the vapour zone by a vertical pipe which passes through the the horizontal sealed partitions and the high pressure zone. The single-loop nuclear power plant is provided with an electric motor to rotate the impeller.