公开(公告)号：US06789564B1

公开(公告)日：2004-09-14

申请号：US10426634

申请日：2003-05-01

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: F16L500

CPC classification number: B65H75/4463 ,  B65H75/38 ,  B65H2701/33 ,  F16L3/012 ,  Y10T137/598 ,  Y10T137/6921 ,  Y10T137/6954 ,  Y10T137/698

Abstract: A hose reel includes a reel and a movable curve tube disposed on the center of a tabular rack. A cover is fixed on a lateral side of the rack while a crank is positioned on the other lateral side. A multi-path hose connects to a movable curve tube by a coupling for being wound on the reel through the crank. Thus the hose is pulled out at the desired length for easy use and ideal storage

Abstract translation: 软管卷轴包括设置在平板状架的中心的卷轴和可动曲线管。 盖子固定在齿条的侧面上，而曲柄位于另一侧面。 多通道软管通过联接器连接到可动弯管，用于通过曲柄缠绕在卷轴上。 因此，软管以期望的长度拉出以便于使用和理想的储存

公开(公告)号：US6133597A

公开(公告)日：2000-10-17

申请号：US900560

申请日：1997-07-25

Applicant: Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

Inventor： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC: H01L21/761 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

Abstract translation: 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAM和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与另一方面的相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US5895945A

公开(公告)日：1999-04-20

申请号：US791596

申请日：1997-01-31

Applicant: Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

Inventor： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

IPC: H01L21/8247 ,  H01L27/108

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by the steps comprisingforming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

Abstract translation: 一种具有被绝缘材料覆盖的衬底的MOSFET器件，该器件包括电容耦合到多晶硅电极的多个掩埋导体，所述多个掩埋导体通过以下步骤形成，所述步骤包括：在包含MOSFET器件的区域之间形成具有衬底中的多个位线的区域， 以预定图案将栅极氧化物注入到衬底中，并且在穿过位线的电介质材料上形成多晶硅电极。

公开(公告)号：US5541876A

公开(公告)日：1996-07-30

申请号：US251972

申请日：1994-06-01

Applicant: Chen-Chin Hsue ,  Ming-Tzong Yang ,  Chung-Cheng Wu

Inventor： Chen-Chin Hsue ,  Ming-Tzong Yang ,  Chung-Cheng Wu

IPC: G11C17/12 ,  H01L27/112 ,  G11C11/34

CPC classification number: G11C17/12 ,  H01L27/112

Abstract: A memory cell and a process for making it are disclosed. The ROM code is not implanted in the floating gate for cells selected to be "off". This memory cell has a much lower threshold voltage than conventional cells and the implantation induced crystal damage is avoided.

Abstract translation: 公开了一种存储单元及其制造方法。 对于选择为“关闭”的单元，ROM码不会植入浮动门。 该存储单元具有比常规电池低得多的阈值电压，并且避免了注入诱导的晶体损伤。

公开(公告)号：US20130130456A1

公开(公告)日：2013-05-23

申请号：US13722142

申请日：2012-12-20

Applicant: Chung-Cheng WU ,  Ali KESHAVARZI ,  Fung Ka HING ,  Ta-Pen GUO ,  Jiann-Tyng TZENG ,  Yen-Ming CHEN ,  Shyue-Shyh LIN ,  Shyh-Wei WANG ,  Sheng-Jier YANG ,  Hsiang-Jen TSENG ,  David B. Scott ,  Min CAO

Inventor： Chung-Cheng WU ,  Ali KESHAVARZI ,  Fung Ka HING ,  Ta-Pen GUO ,  Jiann-Tyng TZENG ,  Yen-Ming CHEN ,  Shyue-Shyh LIN ,  Shyh-Wei WANG ,  Sheng-Jier YANG ,  Hsiang-Jen TSENG ,  David B. Scott ,  Min CAO

IPC: H01L29/66

CPC classification number: H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/7848 ,  H01L2224/16225

Abstract: A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.

Abstract translation: 一种形成集成电路的方法，包括在衬底上形成第一扩散区域和第二扩散区域，其中所述第一扩散区域被配置为用于第一类型晶体管，所述第二扩散区域被配置为用于第二类型晶体管。 该方法还包括在第一扩散区域中形成第一源区和漏区。 该方法还包括在第二扩散区域中形成第二源区和漏区。 该方法还包括形成跨越第一扩散区域和第二扩散区域延伸的栅电极。 该方法还包括形成第一金属层，第二金属层和第三金属层。 第一金属层与第一源区电耦合。 第二金属层与第一和第二漏极区域电耦合。 第三金属层与第二源极区域电耦合。

公开(公告)号：US08357579B2

公开(公告)日：2013-01-22

申请号：US13042539

申请日：2011-03-08

Applicant: King-Yuen Wong ,  Ming-Lung Cheng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

Inventor： King-Yuen Wong ,  Ming-Lung Cheng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

IPC: H01L21/335 ,  H01L21/336 ,  H01L29/76 ,  H01L21/02

CPC classification number: H01L29/7833 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.

Abstract translation: 形成集成电路的方法包括在衬底上形成栅极结构。 去除基板的一部分以形成与栅极结构相邻的凹部。 在每个凹部的侧壁和底部形成有具有第一类型掺杂剂的富掺杂层。 在每个凹部中形成含硅材料结构。 含硅材料结构具有第二种掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20120086053A1

公开(公告)日：2012-04-12

申请号：US12900626

申请日：2010-10-08

Applicant: Chih-Hung TSENG ,  Da-Wen LIN ,  Chien-Tai CHAN ,  Chia-Pin LIN ,  Li-Wen WENG ,  An-Shen CHANG ,  Chung-Cheng WU

Inventor： Chih-Hung TSENG ,  Da-Wen LIN ,  Chien-Tai CHAN ,  Chia-Pin LIN ,  Li-Wen WENG ,  An-Shen CHANG ,  Chung-Cheng WU

IPC: H01L29/78 ,  H01L21/76

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7853

Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

Abstract translation: 晶体管包括覆盖在浅沟槽隔离层下面的切口鳍。 可以使用一个或多个凹口，其尺寸可以沿翅片的横向方向变化。 在一些实施例中，使用根据硅取向选择性的各向异性湿蚀刻形成凹口。 实例湿蚀刻剂是氢氧化四甲基铵（TMAH）或氢氧化钾（KOH）。

公开(公告)号：US20110248322A1

公开(公告)日：2011-10-13

申请号：US12758568

申请日：2010-04-12

Applicant: King-Yuen Wong ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

Inventor： King-Yuen Wong ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/513 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7843

Abstract: An embodiment is a semiconductor device. The semiconductor device comprises a substrate, an electrode over the substrate, and a piezoelectric layer disposed between the substrate and the electrode. The piezoelectric layer causes a strain in the substrate when an electric field is generated by the electrode.

Abstract translation: 一个实施例是半导体器件。 半导体器件包括衬底，衬底上的电极以及设置在衬底和电极之间的压电层。 当电极产生电场时，压电层在衬底中引起应变。

公开(公告)号：US20070224808A1

公开(公告)日：2007-09-27

申请号：US11387614

申请日：2006-03-23

Applicant: Tsung-Hsien Chang ,  Tung-Heng Hsieh ,  Chung-Cheng Wu ,  Shou Chang

Inventor： Tsung-Hsien Chang ,  Tung-Heng Hsieh ,  Chung-Cheng Wu ,  Shou Chang

IPC: H01L21/4763

CPC classification number: H01L29/665 ,  H01L21/31111 ,  H01L29/6653

Abstract: A silicided gate for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate. A first dielectric layer is formed over the gate electrode and the substrate, and a second dielectric layer is formed over the first dielectric layer. The second dielectric layer is etched to form spacers adjacent the gate electrode. A treatment is performed on the first dielectric layer over the gate electrode, wherein the treatment increases the effective etch rate of the first dielectric layer as compared to untreated portions of the first dielectric layer. An etching procedure is then performed to expose the surface of the gate electrode, the etching procedure recessing the liner along sidewalls of the gate electrode. Thereafter, a silicide procedure is performed to silicide at least a portion of the gate electrode.

Abstract translation: 提供了用于CMOS晶体管的硅化物栅极和制造方法。 在基板上形成栅电极。 在栅电极和衬底之上形成第一电介质层，并且在第一介电层上形成第二电介质层。 蚀刻第二电介质层以形成邻近栅极的间隔物。 在栅电极上的第一电介质层上进行处理，其中与第一介电层的未处理部分相比，处理增加了第一介电层的有效蚀刻速率。 然后执行蚀刻过程以暴露栅电极的表面，蚀刻过程使衬垫沿着栅电极的侧壁凹陷。 此后，执行硅化物步骤以对栅电极的至少一部分进行硅化。

公开(公告)号：US20060055289A1

公开(公告)日：2006-03-16

申请号：US10937326

申请日：2004-09-10

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: A47G29/00

CPC classification number: F16B12/32 ,  A47B47/0016 ,  A47F7/0078 ,  A47G7/041

Abstract: A combinational gardening rack comprising several frames, several combining connectors and a hood; the major feature of the present invention is that the combining connectors have vertical and horizontal connecting holes with same diameter, the vertical connecting hole is hollow in center, a wedge stretches out from the bottom of the vertical connecting hole, a locking mechanism is on the wedge. While assembly based on the structure described above, users can apply the wedges and locking mechanisms to assemble the frames and the combining connectors together at any height on the vertical frames, such scheme can adjust the height between layers of the rack.

Abstract translation: 组合式园艺架，包括几个框架，多个组合连接器和罩; 本发明的主要特征在于，组合连接器具有直径相同的垂直和水平连接孔，垂直连接孔在中心是中空的，楔形件从垂直连接孔的底部伸出，锁定机构位于 楔。 在基于上述结构的组装时，用户可以应用楔形和锁定机构将框架和组合连接器组装在垂直框架上的任何高度处，这种方案可以调节机架的层之间的高度。