公开(公告)号：US20210119118A1

公开(公告)日：2021-04-22

申请号：US17109318

申请日：2020-12-02

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Sarin A. DESHPANDE

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

公开(公告)号：US20210111223A1

公开(公告)日：2021-04-15

申请号：US17131926

申请日：2020-12-23

Applicant: Everspin Technologies, Inc.

Inventor： Jijun SUN ,  Sanjeev AGGARWAL ,  Han-Jong CHIA ,  Jon M. SLAUGHTER ,  Renu WHIG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  G11B5/39 ,  H01L43/10

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

公开(公告)号：US20210083174A1

公开(公告)日：2021-03-18

申请号：US16572982

申请日：2019-09-17

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry Joseph NAGEL

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.

公开(公告)号：US10910434B2

公开(公告)日：2021-02-02

申请号：US16870099

申请日：2020-05-08

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Sanjeev Aggarwal ,  Han-Jong Chia ,  Jon M. Slaughter ,  Renu Whig

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  G11B5/39 ,  H01L43/10

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

公开(公告)号：US10886331B2

公开(公告)日：2021-01-05

申请号：US16380207

申请日：2019-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A method of manufacturing a magnetoresistive device may include forming a first ferromagnetic region, forming an intermediate region on or above the first ferromagnetic region. The intermediate region may be formed of a dielectric material and include nitrogen. The method may also include forming a second ferromagnetic region on or above the intermediate region.

公开(公告)号：US10825500B2

公开(公告)日：2020-11-03

申请号：US16286793

申请日：2019-02-27

Applicant: Everspin Technologies, Inc.

Inventor： Han-Jong Chia ,  Sumio Ikegawa ,  Michael Tran ,  Jon Slaughter

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  H01L43/10 ,  G11C11/56

Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.

公开(公告)号：US10794968B2

公开(公告)日：2020-10-06

申请号：US15685085

申请日：2017-08-24

Applicant: Everspin Technologies, Inc.

Inventor： Jon Slaughter

IPC: G01R33/09 ,  H01L27/22 ,  G01R33/00 ,  H01L43/12 ,  G01R35/00

Abstract: A magnetic field sensor that includes a differential bridge in which each path of the bridge includes a first type of magnetic field sensing device and a second type of magnetic field sensing device. The first and second types of magnetic field sensing devices differ in the magnetic moment imbalance present in the synthetic antiferromagnets (SAFs) included in their reference layers such that that different types of devices produce a different response to perpendicular magnetic fields, but the same response to in-plane magnetic fields. Such different magnetic moment imbalances in the SAFs of magnetic field sensing devices included in a bridge allow for accurate sensing of perpendicular magnetic fields in a differential manner that also cancels out interference from in-plane fields. Techniques for producing such magnetic field sensing devices on an integrated circuit are also presented. Moreover, the free layers within the magnetic field sensing devices can be adjusted in terms of their sensitivity range and level of sensitivity by manipulating the kink filed (Hk) for those free layers.

公开(公告)号：US20200235289A1

公开(公告)日：2020-07-23

申请号：US16251230

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Thomas ANDRE ,  Frederick MANCOFF ,  Sumio IKEGAWA

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.

公开(公告)号：US10658575B2

公开(公告)日：2020-05-19

申请号：US15808996

申请日：2017-11-10

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel

IPC: H01L43/12 ,  H01L23/544 ,  H01L43/02 ,  H01L43/08

Abstract: Techniques are presented for ensuring alignment marks are available for use and patterning magnetoresistive devices following the deposition of layers used to form the magnetoresistive devices. In some cases, the plurality of layers corresponding to the magnetoresistive devices are selectively etched in order to expose the underlying alignment marks, whereas in other embodiments, the deposition of the plurality of layers is controlled by deposition tool tabs that prevent the materials from obscuring the underlying alignment marks.

公开(公告)号：US10657014B2

公开(公告)日：2020-05-19

申请号：US15901330

申请日：2018-02-21

Applicant: Everspin Technologies, Inc.

Inventor： Kurt Baty ,  Terry Van Hulett

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G11C29/00 ,  G11C29/44 ,  G06F11/07 ,  G06F11/30

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes scanning a first memory region for bit errors; in response to detecting one or more bit errors in the first memory region, incrementing a counter associated with the first memory region based on the number of bit errors detected; comparing a total number of bit errors against a threshold, wherein the total number of bit errors is identified from the first counter; and, if the total number of bit errors exceeds the threshold, restricting access to the first memory region by mapping an address corresponding to the first memory region to a second memory region.