公开(公告)号：US20110163365A1

公开(公告)日：2011-07-07

申请号：US13050052

申请日：2011-03-17

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： H01L27/092 ,  H01L21/02

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

公开(公告)号：US07965540B2

公开(公告)日：2011-06-21

申请号：US12055509

申请日：2008-03-26

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： G11C11/412

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

公开(公告)号：US20110102042A1

公开(公告)日：2011-05-05

申请号：US12987106

申请日：2011-01-08

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US20090134925A1

公开(公告)日：2009-05-28

申请号：US11857596

申请日：2007-09-19

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： H03K3/356 ,  H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US08300452B2

公开(公告)日：2012-10-30

申请号：US13050052

申请日：2011-03-17

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： G11C11/00

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

公开(公告)号：US08138573B2

公开(公告)日：2012-03-20

申请号：US12766342

申请日：2010-04-23

申请人： Ethan H. Cannon ,  Alvin W. Strong

发明人： Ethan H. Cannon ,  Alvin W. Strong

IPC分类号： H01L31/115

CPC分类号： H01L23/345 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

摘要翻译： 片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。 该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。

公开(公告)号：US08133772B2

公开(公告)日：2012-03-13

申请号：US13075271

申请日：2011-03-30

申请人： John E. Barth, Jr. ,  Kerry Bernstein ,  Ethan H. Cannon ,  Francis R. White

发明人： John E. Barth, Jr. ,  Kerry Bernstein ,  Ethan H. Cannon ,  Francis R. White

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

公开(公告)号：US20110309856A1

公开(公告)日：2011-12-22

申请号：US13015331

申请日：2011-01-27

申请人： Manuel F. Cabanas-Holmen ,  Ethan H. Cannon ,  Salim A. Rabaa

发明人： Manuel F. Cabanas-Holmen ,  Ethan H. Cannon ,  Salim A. Rabaa

IPC分类号： H03K19/003 ,  G06F17/50

CPC分类号： G11C5/005 ,  G11C7/02 ,  H03K3/0375 ,  H03K3/356121 ,  H03K17/693

摘要： The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

公开(公告)号：US07943482B2

公开(公告)日：2011-05-17

申请号：US12186762

申请日：2008-08-06

申请人： John M. Aitken ,  Ethan H. Cannon

发明人： John M. Aitken ,  Ethan H. Cannon

IPC分类号： H01L21/76 ,  G06F17/50

CPC分类号： H01L23/556 ,  H01L21/76283 ,  H01L23/481 ,  H01L23/585 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00

摘要： A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure includes: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.

摘要翻译： 提供了一种在SOI技术中具有辐射硬化掩埋绝缘体和隔离绝缘体的半导体器件的设计结构。 该装置包括第一结构和第二结构。 第一结构包括：有源器件层下方的辐射硬化BOX层; 在有源器件层的有源区和辐射硬化BOX层之上的辐射硬化浅沟槽隔离（STI）结构; 在有源区域的栅极结构之上的一个或多个层间电介质层中的金属互连。 第二结构被结合到第一结构。 第二结构包括：基于硅的衬底; 衬底上的BOX层; BOX上有活性区的Si层; 在Si层的有源区之间的氧化物填充的STI结构; 以及栅极结构之上的一个或多个层间电介质层中的金属互连。 至少一个金属互连件将第一结构电连接到第二结构。

公开(公告)号：US07881135B2

公开(公告)日：2011-02-01

申请号：US11679406

申请日：2007-02-27

申请人： Ethan H. Cannon ,  Alan J. Drake ,  Fadi H. Gebara ,  John P. Keane ,  AJ Kleinosowski

发明人： Ethan H. Cannon ,  Alan J. Drake ,  Fadi H. Gebara ,  John P. Keane ,  AJ Kleinosowski

IPC分类号： G11C29/00

CPC分类号： G01R31/318594 ,  G01R31/318597

摘要： A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.

摘要翻译： 用于估计被测电路的临界电荷的测试装置（CUT）使用具有选择性地连接到CUT的节点的开关电容器的电荷注入电路。 电压测量电路测量电荷注入前后电荷注入电路中的电压。 当注入的电荷导致CUT的逻辑状态不正常时，临界电荷被计算为电压差和电容器的已知电容的乘积。 在一个实施例中，（NMOS漏极击穿模拟）通过门控电荷注入电路的开关的可变脉冲宽度发生器来控制注入的电荷量。 在另一实施例（PMOS漏极击穿模拟）中，注入的电荷量由选择性地连接到电荷存储节点的可变电压电源来控制。