公开(公告)号：US08563411B2

公开(公告)日：2013-10-22

申请号：US13191948

申请日：2011-07-27

Applicant: Ha-Jin Lim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

Inventor： Ha-Jin Lim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L21/3205

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4966

Abstract: Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.

公开(公告)号：US20120034752A1

公开(公告)日：2012-02-09

申请号：US13195521

申请日：2011-08-01

Applicant: Weon-Hong KIM ,  Hyung-Suk Jung ,  Ha-Jin Lim

Inventor： Weon-Hong KIM ,  Hyung-Suk Jung ,  Ha-Jin Lim

IPC: H01L21/336 ,  H01L21/02

CPC classification number: H01L21/28247 ,  H01L21/823425 ,  H01L27/10873 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/78

Abstract: In a method of forming a gate structure, a gate pattern including a gate insulation layer pattern and a gate electrode sequentially stacked on a substrate is formed. The gate electrode includes a metal. A first plasma process is performed on the gate pattern using a reaction gas to reduce an oxidized edge portion of the gate electrode. The reaction gas includes nitrogen. A spacer is formed on a sidewall of the gate pattern. A threshold voltage is adjusted by reducing the oxidized edge portion of the gate electrode. Therefore, a semiconductor device including the gate pattern has excellent electrical characteristics.

Abstract translation: 在形成栅极结构的方法中，形成包括依次层叠在基板上的栅极绝缘层图案和栅电极的栅极图案。 栅电极包括金属。 使用反应气体对栅极图案进行第一等离子体处理，以减少栅电极的氧化边缘部分。 反应气体包括氮气。 在栅极图案的侧壁上形成间隔物。 通过减小栅电极的氧化边缘部分来调节阈值电压。 因此，包括栅极图案的半导体器件具有优异的电气特性。

公开(公告)号：US20110306171A1

公开(公告)日：2011-12-15

申请号：US13105652

申请日：2011-05-11

Applicant: Ha-Jin Lim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

Inventor： Ha-Jin Lim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L29/518

Abstract: An insulation layer is formed on a substrate having an NMOS region and a PMOS region defined therein. A first conductive layer is formed on the insulation layer in the PMOS region, leaving a portion of the insulation layer in the NMOS region exposed. Nitriding is performed to produce a first nitrogen concentration in the insulation layer in the NMOS region and a second nitrogen concentration less than the first nitrogen concentration in the insulation layer in the PMOS region. A second conductive layer is formed on the insulation layer and the first conductive layer and the first and second conductive layers and the insulation layer are patterned to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively.

Abstract translation: 在其上限定有NMOS区和PMOS区的基板上形成绝缘层。 在PMOS区域中的绝缘层上形成第一导电层，使NMOS区域中的绝缘层的一部分露出。 进行氮化，以在NMOS区域中的绝缘层中产生第一氮浓度，并且在PMOS区域中的绝缘层中小于第一氮浓度的第二氮浓度。 第二导电层形成在绝缘层上，并且第一导电层以及第一和第二导电层和绝缘层被图案化以分别在NMOS区域和PMOS区域中形成第一栅极结构和第二栅极结构。

公开(公告)号：US07952118B2

公开(公告)日：2011-05-31

申请号：US11946153

申请日：2007-11-28

Applicant: Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ha-jin Lim

Inventor： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ha-jin Lim

IPC: H01L29/78

CPC classification number: H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02362 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31645 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.

Abstract translation: 半导体包括半导体衬底中的沟道区域，沟道区上的栅极电介质膜和栅极电介质膜上的栅极。 栅极包括由第一金属的氮化物形成并掺杂有与第一金属不同的第二金属的掺杂金属氮化物膜和形成在掺杂金属氮化物膜上的导电多晶硅层。 栅极还可以包括插入在掺杂的金属氮化物膜和导电多晶硅层之间的含金属的覆盖层。

公开(公告)号：US20100171182A1

公开(公告)日：2010-07-08

申请号：US12652426

申请日：2010-01-05

Applicant: Dong-Suk Shin ,  Pan-Kwi Park ,  Ha-Jin Lim ,  Joo-Chan Kim

Inventor： Dong-Suk Shin ,  Pan-Kwi Park ,  Ha-Jin Lim ,  Joo-Chan Kim

IPC: H01L27/092 ,  H01L21/3115

CPC classification number: H01L21/823412 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

Abstract: A strained semiconductor device includes a first plurality of transistors spaced with a first gate pitch, a second plurality of transistors spaced with a second gate pitch greater than the first gate pitch, and an etch stop layer disposed on the first and second pluralities of transistors. The etch stop layer between each of the second plurality of transistors has a greater proportion of a stress-altering material than the etch stop layer between each of the first plurality of transistors.

Abstract translation: 应变半导体器件包括与第一栅极间隔开的第一多个晶体管，与第一栅极间距大于第二栅极间隔的第二多个晶体管，以及设置在第一和第二多个晶体管上的蚀刻停止层。 第二多个晶体管中的每一个之间的蚀刻停止层具有比在第一多个晶体管中的每一个之间的蚀刻停止层更大的应力改变材料的比例。

公开(公告)号：US20080261360A1

公开(公告)日：2008-10-23

申请号：US12019449

申请日：2008-01-24

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28026 ,  H01L29/49

Abstract: In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.

Abstract translation: 在制造半导体器件的方法中，在包括第一导电类型的第一沟道和不同于第一导电类型的第二导电类型的第二沟道的衬底上形成栅极绝缘层。 在栅极绝缘层上形成包括第一金属的第一导电层，并且在形成在第二沟道上的第一导电层上形成包括不同于第一金属的第二金属的第二导电层。 通过湿式蚀刻工艺部分去除第二导电层，以在第二通道上形成第二导电层图案。

公开(公告)号：US07396777B2

公开(公告)日：2008-07-08

申请号：US11107559

申请日：2005-04-15

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Ha-Jin Lim ,  Jae-Eun Park ,  Yun-Seok Kim ,  Jong-Ho Yang

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Ha-Jin Lim ,  Jae-Eun Park ,  Yun-Seok Kim ,  Jong-Ho Yang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/022 ,  C23C16/402 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/45529 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.

Abstract translation: 公开了制造用于半导体应用的具有减少的杂质的高k电介质层的方法。 该方法包括以下步骤：结合对叠层电介质层执行的后处理步骤，使用ALD法形成具有形成在半导体衬底上的第一电介质层和第二电介质层的叠层电介质层。 形成堆叠的电介质层并进行后处理的步骤至少重复一次，从而制造高k电介质层。

公开(公告)号：US20080079086A1

公开(公告)日：2008-04-03

申请号：US11831069

申请日：2007-07-31

Applicant: Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ho Lee ,  Ha-jin Lim

Inventor： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ho Lee ,  Ha-jin Lim

IPC: H01L21/336 ,  H01L27/085

CPC classification number: H01L21/823807

Abstract: A semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device includes a semiconductor substrate in which PMOS transistor regions and NMOS transistor regions are formed, a PMOS transistor including P-type source and drain regions and a gate electrode, and an NMOS transistor formed on an Si channel region between N-type source and drain regions. The PMOS transistor is formed in each PMOS transistor region, and the gate electrode is formed on a high-dielectric gate insulating film formed on an SiGe channel region between the P-type source and drain regions. Further, the NMOS transistor includes a high-dielectric gate insulating film and a gate electrode formed on the gate insulating film, and the NMOS transistor is formed in each NMOS transistor region.

Abstract translation: 一种半导体器件和半导体器件的制造方法，其中半导体器件包括其中形成有PMOS晶体管区域和NMOS晶体管区域的半导体衬底，包括P型源极和漏极区域的PMOS晶体管和栅极电极，以及 形成在N型源区和漏区之间的Si沟道区上的NMOS晶体管。 PMOS晶体管形成在每个PMOS晶体管区域中，并且栅电极形成在形成在P型源区和漏区之间的SiGe沟道区上的高电介质栅极绝缘膜上。 此外，NMOS晶体管包括高电介质栅极绝缘膜和形成在栅极绝缘膜上的栅电极，并且NMOS晶体管形成在每个NMOS晶体管区域中。

公开(公告)号：US20050255246A1

公开(公告)日：2005-11-17

申请号：US11127748

申请日：2005-05-12

Applicant: Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

Inventor： Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

IPC: C23C16/00 ,  C23C16/40 ,  C23C16/455

CPC classification number: C23C16/401 ,  C23C16/45529 ,  C23C16/45531

Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor. The silicon oxide layer formation cycle includes supplying a silicon source gas, exhausting the silicon source gas remaining in the reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.

Abstract translation: 提供了使用原子层沉积技术在半导体衬底上制造金属硅酸盐层的方法。 所述方法包括至少一次执行金属硅酸盐层形成循环以形成具有所需厚度的金属硅酸盐层。 金属硅酸盐层形成循环包括重复执行金属氧化物层形成循环K次的操作和重复进行氧化硅层形成循环Q次的操作。 K和Q分别为1〜10的整数。 金属氧化物层形成循环包括将金属源气体供给到含有基板的反应器，排出留在反应器内的金属源气体，清洗反应器内部，然后向反应器供给氧化气体的工序。 氧化硅层形成循环包括提供硅源气体，排出留在反应器中的硅源气体以清洁反应器的内部，然后将氧化物气体供应到反应器中。

公开(公告)号：US08877579B2

公开(公告)日：2014-11-04

申请号：US13417787

申请日：2012-03-12

Applicant: Moon-kyun Song ,  Ha-jin Lim ,  Moon-han Park ,  Jin-ho Do

Inventor： Moon-kyun Song ,  Ha-jin Lim ,  Moon-han Park ,  Jin-ho Do

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823807

Abstract: Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.

Abstract translation: 制造半导体器件的方法包括提供包括NMOS区域和PMOS区域的衬底，将氟离子注入到衬底的上表面中，形成NMOS区域的第一栅极电极和衬底上的PMOS区域的第二栅极电极 在所述基板的与所述第一栅电极和所述第二栅电极的两个侧面相邻的部分分别形成源极区域和漏极区域，并在所述第一栅极电极和所述第二栅极电极的上表面上进行高压热处理工序 通过使用非氧化性气体的基板。