公开(公告)号：US08791771B2

公开(公告)日：2014-07-29

申请号：US13298489

申请日：2011-11-17

Applicant: Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, Jr. ,  Jiansheng Xu

Inventor： Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, Jr. ,  Jiansheng Xu

IPC: H01P5/12 ,  H03L5/00

CPC classification number: H01P5/16

Abstract: A reconfigurable Wilkinson power divider, methods of manufacture and design structures are provided. The structure includes a first port, and a first arm and a second arm connected to the first port. The first arm and the second arm each include one or more tunable t-line circuits. The structure also includes a second port and a third port connected to the first port via the first arm and second arm, respectively.

Abstract translation: 提供可重构的Wilkinson功率分配器，制造和设计结构的方法。 该结构包括第一端口和连接到第一端口的第一臂和第二臂。 第一臂和第二臂各包括一个或多个可调t线电路。 该结构还包括分别经由第一臂和第二臂连接到第一端口的第二端口和第三端口。

公开(公告)号：US08645898B2

公开(公告)日：2014-02-04

申请号：US13535412

申请日：2012-06-28

Applicant: Hanyi Ding ,  Mete Erturk ,  Robert A. Groves ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Anthony K. Stamper

Inventor： Hanyi Ding ,  Mete Erturk ,  Robert A. Groves ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC: G06F17/50 ,  H01L27/08

CPC classification number: H01L28/10 ,  H01L21/76898 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

Abstract translation: 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。

公开(公告)号：US08446014B2

公开(公告)日：2013-05-21

申请号：US13531008

申请日：2012-06-22

Applicant: Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

Inventor： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

IPC: H01L23/48

CPC classification number: H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract translation: 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

公开(公告)号：US08421183B2

公开(公告)日：2013-04-16

申请号：US13016126

申请日：2011-01-28

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L23/552 ,  H01L21/76 ,  H01L21/76264 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

公开(公告)号：US08413098B2

公开(公告)日：2013-04-02

申请号：US12431887

申请日：2009-04-29

Applicant: Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne Harvey Woods, Jr.

Inventor： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne Harvey Woods, Jr.

IPC: G06F17/50

CPC classification number: H01L23/5225 ,  G06F17/5036 ,  G06F17/5063 ,  G06F17/5072 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.

Abstract translation: T型连接，T型连接的设计方法和T型连接的紧凑建模。 T形连接件包括一个导电T形接头，它包括主体和从本体的相互垂直的侧面突出的第一，第二和第三整体臂，三个整体臂的每个臂具有与主体相邻的相同的第一宽度和相同的长度 远离身体; 导电性阶梯结，其包括具有第一宽度的第一部分和具有第二宽度的整体和邻接的第二部分，所述第二宽度不同于所述第一宽度，所述第一部分平滑地抵接并与所述第二部分 交界处 并且其中T形结和台阶结的顶表面是共面的。

公开(公告)号：US08338920B2

公开(公告)日：2012-12-25

申请号：US11690682

申请日：2007-05-08

Applicant: John Michael Cotte ,  Hanyi Ding ,  Kai Di Feng ,  Zhong-Xiang He ,  Nils D. Hoivik ,  Xuefeng Liu

Inventor： John Michael Cotte ,  Hanyi Ding ,  Kai Di Feng ,  Zhong-Xiang He ,  Nils D. Hoivik ,  Xuefeng Liu

IPC: H01L23/552

CPC classification number: H01L23/04 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/645 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01042

Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.

Abstract translation: 集成电路封装包括具有一个或多个片上电感器的集成电路。 封装盖覆盖集成电路。 磁性材料设置在集成电路和封装盖之间。 磁性材料可以是软磁性薄膜。 磁性材料可以通过粘合剂固定到包装盖上。 磁性材料可以通过沉积，溅射或喷涂之一直接形成在封装盖上。 磁性材料可以固定在集成电路上。

公开(公告)号：US20120267794A1

公开(公告)日：2012-10-25

申请号：US13535412

申请日：2012-06-28

Applicant: Hanyi DING ,  Mete ERTURK ,  Robert A. GROVES ,  Zhong-Xiang HE ,  Peter J. LINDGREN ,  Anthony K. STAMPER

Inventor： Hanyi DING ,  Mete ERTURK ,  Robert A. GROVES ,  Zhong-Xiang HE ,  Peter J. LINDGREN ,  Anthony K. STAMPER

IPC: H01L23/48

CPC classification number: H01L28/10 ,  H01L21/76898 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

Abstract translation: 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口的多个垂直开口中的第二个 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。

公开(公告)号：US20120266116A1

公开(公告)日：2012-10-18

申请号：US13534350

申请日：2012-06-27

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

IPC: G06F17/50

CPC classification number: H01Q1/2283 ,  H01Q1/40 ,  H01Q9/26 ,  H01Q9/285 ,  H01Q19/108 ,  H01Q19/30

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

Abstract translation: 提供集成收发器，天线和接收器的半导体芯片。 收发器位于半导体衬底的前侧。 通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。 连接到收发器的天线位于位于基板正面的电介质层中。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。 还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

公开(公告)号：US08279572B2

公开(公告)日：2012-10-02

申请号：US12144095

申请日：2008-06-23

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: H02H9/02

CPC classification number: H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.

Abstract translation: 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。 其中形成有多于一个电极的第二电介质层位于第一介电层的上方。 至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。 通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。 第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

公开(公告)号：US20120212303A1

公开(公告)日：2012-08-23

申请号：US13455725

申请日：2012-04-25

Applicant: Hanyi DING ,  Alvin J. JOSEPH ,  Wayne H. WOODS, JR.

Inventor： Hanyi DING ,  Alvin J. JOSEPH ,  Wayne H. WOODS, JR.

IPC: H01P5/12 ,  G06F17/50 ,  H01L27/08

CPC classification number: G06F17/5077 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P5/16 ,  H01P11/007 ,  H01L2924/00

Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

Abstract translation: 一种通过硅通孔威尔金森功率分配器的方法，结构和设计结构。 一种方法包括：在基板的第一侧上形成输入; 形成包括在所述基板中形成的第一穿通硅通孔的第一支脚，其中所述第一支路电连接所述输入端和第一输出端; 形成包括形成在所述基板中的第二通硅通孔的第二支脚，其中所述第二支脚电连接所述输入端和第二输出端，以及形成电连接在所述第一输出端和所述第二输出端之间的电阻器。