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37 条记录 (耗时 0.015 秒)

    Memory circuit
    22.
    发明授权
    Memory circuit 失效
    存储电路

    公开(公告)号：US5295094A

    公开(公告)日：1994-03-15

    申请号：US794268

    申请日：1991-11-19

    申请人： Hideshi Miyatake

    发明人： Hideshi Miyatake

    IPC分类号： G11C11/409 ,  G11C7/06

    CPC分类号： G11C7/062

    摘要： A memory circuit incorporating a current-mirror type amplifier which directly amplifies a varied potential of a pair of bit lines. As soon as the word line goes High, the current-mirror type amplifier is simultaneously activated to amplify a minimal difference (100 mV) of potential between these bit lines. Data signal outputted from the current-mirror type amplifier is then transmitted to a read-only signal line. As a result, data is quickly read out before a built-in sense amplifier completes amplification, thus quickly achieving an accessing operation at extremely fast speed.

    摘要翻译： 一种结合电流镜型放大器的存储电路，其直接放大一对位线的变化电位。 只要字线为高电平，电流镜式放大器就会同时被激活，以放大这些位线之间的最小电位差（100 mV）。 然后将从电流镜型放大器输出的数据信号发送到只读信号线。 因此，在内置的读出放大器完成放大之前，可以快速读出数据，从而以极快的速度快速实现访问操作。

    Dynamic random access memory with dummy word lines connected to bit line potential adjusting capacitors
    23.
    发明授权
    Dynamic random access memory with dummy word lines connected to bit line potential adjusting capacitors 失效
    具有连接到位线电位调整电容器的虚拟字线的动态随机存取存储器

    公开(公告)号：US5255235A

    公开(公告)日：1993-10-19

    申请号：US859269

    申请日：1992-03-25

    申请人： Hideshi Miyatake

    发明人： Hideshi Miyatake

    IPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C11/407

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A dynamic random access memory (DRAM) having a plurality of word lines and a plurality of bit line pairs comprises circuitry for applying an equalizing potential to either one or the other bit line of the paired bit lines to equalize (1) a first difference between a first potential and a second potential and (2) a second difference between the first potential and a third potential, for balanced read out of the paired bit lines. The first potential appears on a reference bit line paired with a bit line connected to a memory cell selected by an external address prior to sensing thereof, the second potential appears on the bit line when the selected memory cell contains "H" level data and the third potential appears on the bit line when the selected memory cell contains "L" level data. Each bit line pair has circuitry for adjusting bit line potentials consisting of a pair of capacitors having their electrodes connected to respective bit lines of an associated bit line pair in a corresponding column, and a pair of dummy word lines running parallel to the plurality of word lines, connected to respective other electrodes of the pair of capacitors. When a memory cell, connected to a bit line in a bit line pair, is selected, the potential of a dummy word line capacitively coupled to the other bit line in the bit line pair is rendered active before a sense amplifier is made active for a sensing operation.

    摘要翻译： 具有多个字线和多个位线对的动态随机存取存储器（DRAM）包括用于将均衡电位施加到成对位线的任一位或另一位线的电路，以使（1） 第一电位和第二电位，以及（2）第一电位和第三电位之间的第二差，用于平衡读出成对的位线。 第一个电位出现在与感测它之前由连接到由外部地址选择的存储单元的位线配对的参考位线上，当所选存储单元包含“H”电平数据时，第二电位出现在位线上，并且 当选择的存储单元包含“L”电平数据时，位线上出现第三个电位。 每个位线对具有用于调整位线电位的电路，该位线电位由一对电容器组成，该电容器的电极连接到相应列中相关联的位线对的相应位线，以及一对平行于多个字的虚拟字线 线，连接到该对电容器的各个其他电极。 当连接到位线对中的位线的存储单元被选择时，在将读出放大器激活到位线对之前，电容性耦合到位线对中的另一个位线的虚拟字线的电位被激活 感测操作。

    Semiconductor memory device with improved immunity to supply voltage fluctuations
    24.
    发明授权
    Semiconductor memory device with improved immunity to supply voltage fluctuations 失效
    半导体存储器件具有改善的抗电压供应电压波动

    公开(公告)号：US4903238A

    公开(公告)日：1990-02-20

    申请号：US201787

    申请日：1988-06-02

    申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Katsumi Dosaka

    发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Katsumi Dosaka

    IPC分类号： G11C11/41 ,  G11C5/14 ,  G11C11/409 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C5/14

    摘要： A semiconductor memory device such as a static RAM (Random Access Memory) device comprises a ground connection circuit of n channel field effect transistors connected between two I/O lines and the ground. The precharge circuit for precharging and the ground connection circuit both operate in response to the signal which is in synchronization with an externally applied external chip select signal. Therefore, the access delay derived from the fluctuation of the supply voltage generated before the change of the external chip select signal can be prevented.

    摘要翻译： 诸如静态RAM（随机存取存储器）装置的半导体存储器件包括连接在两个I / O线和地之间的n沟道场效应晶体管的接地连接电路。 用于预充电的预充电电路和接地连接电路都响应于与外部施加的外部芯片选择信号同步的信号而工作。 因此，可以防止在外部芯片选择信号改变之前产生的电源电压的波动导致的访问延迟。

    On-chip substrate bias generating circuit having substrate potential clamp and operating method therefor
    25.
    发明授权
    On-chip substrate bias generating circuit having substrate potential clamp and operating method therefor 失效
    具有衬底电位钳位的片上衬底偏置产生电路及其操作方法

    公开(公告)号：US4890011A

    公开(公告)日：1989-12-26

    申请号：US192576

    申请日：1988-05-11

    申请人： Hideshi Miyatake

    发明人： Hideshi Miyatake

    IPC分类号： G11C11/407 ,  G05F3/20 ,  G11C11/4074

    CPC分类号： G05F3/205 ,  G11C11/4074

    摘要： A semiconductor integrated circuit having a power supply terminal, ground terminal and a substrate bias terminal comprises a substrate voltage generating circuit connected to the power supply terminal and the ground terminal for generating a substrate bias voltage of a predetermined value and for applying the same to the substrate bias terminal, a MOS transistor provided between the substrate bias terminal and the ground terminal for bringing the substrate potential to the ground potential when the supply voltage of the power supply terminal exceeds a prescribed voltage value and a plurality of diode connected MOS transistors connected between the power supply terminal and the gate of the MOS transistor for deciding the prescribed voltage value.

    摘要翻译： 具有电源端子，接地端子和衬底偏置端子的半导体集成电路包括连接到电源端子和接地端子的衬底电压产生电路，用于产生预定值的衬底偏置电压并将其施加到 衬底偏置端子，设置在衬底偏置端子和接地端子之间的MOS晶体管，用于当电源端子的电源电压超过规定电压值时使衬底电位接地，并且多个二极管连接的MOS晶体管连接在 电源端子和用于决定规定电压值的MOS晶体管的栅极。

    Semiconductor memory device with active pull up
    28.
    发明授权
    Semiconductor memory device with active pull up 失效
    具有主动上拉功能的半导体存储器件

    公开(公告)号：US4809230A

    公开(公告)日：1989-02-28

    申请号：US938065

    申请日：1986-12-04

    申请人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

    发明人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

    IPC分类号： G11C11/407 ,  G11C11/34 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/00 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C11/4076 ,  G11C11/4094

    摘要： A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

    摘要翻译： MOS动态型RAM包括存储单元（10），虚设单元（11），位线对（BL，＆amp; B和B），字线（WL），虚拟字线（DWL）和读出放大器（12）。 在非有效周期中，每对位线（BL，＆amp; B和B）的电位在电源电位VCC的1/2处被预充电。 每个读出放大器（12）在非活动周期之后的有效周期中工作，而每个有源上拉电路（13）将该对位线中较高一级的电位上拉至VCC。 该活动周期由内部RAS内部信号定义，该内部RAS内部信号由NAND电路（27）响应于通过延迟电路（20）延迟外部＆upbar＆R信号而获得的外部＆upbar＆R信号和＆upbar＆R信号产生的内部RAS内部信号， 并且具有通过将外部＆upbar＆R信号的后沿延迟预定周期而获得的后沿。

    Dummy word line driving circuit for a MOS dynamic RAM
    29.
    发明授权
    Dummy word line driving circuit for a MOS dynamic RAM 失效
    用于MOS动态RAM的虚拟字线驱动电路

    公开(公告)号：US4757476A

    公开(公告)日：1988-07-12

    申请号：US876912

    申请日：1986-06-20

    申请人： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

    发明人： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

    IPC分类号： G11C11/401 ,  G11C7/14 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4099 ,  G11C7/02

    CPC分类号： G11C7/14 ,  G11C11/4099

    摘要： A dummy word line driving circuit for a MOS dynamic RAM comprises a dummy word line controller connected to each end of a pair of dummy word lines. A sub-decode signal which is opposite to the one inputted to a dummy word driver and a dummy set signal for writing a bit line information into a not-selected dummy cell are inputted to the dummy word line controller. Means for applying a dummy equalizing signal is connected to two full-sized dummy cells, for equalizing the two before the dummy word line is driven. The two full-sized dummy cells are equalized by the signal, resulting in a charge amount, which is to be a reference value, of a half of a full-sized memory cell.

    摘要翻译： 用于MOS动态RAM的虚拟字线驱动电路包括连接到一对虚拟字线的每一端的虚拟字线控制器。 将与输入到虚拟字驱动器的子解码信号相反的子解码信号和用于将位线信息写入未选择的虚拟单元的伪设置信号被输入到虚拟字线控制器。 用于应用虚拟均衡信号的装置连接到两个全尺寸的虚拟小区，用于在虚拟字线被驱动之前均衡两者。 两个全尺寸虚拟单元被信号相等，导致作为参考值的充电量为全尺寸存储单元的一半。