公开(公告)号：US09685206B2

公开(公告)日：2017-06-20

申请号：US13948557

申请日：2013-07-23

Applicant: Myung-Hoon Choi ,  Jae-Yong Jeong ,  Ki-Tae Park

Inventor： Myung-Hoon Choi ,  Jae-Yong Jeong ,  Ki-Tae Park

IPC: G11C7/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/44 ,  G11C29/02 ,  G11C16/00

CPC classification number: G11C7/1057 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44

Abstract: A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.

公开(公告)号：USRE45222E1

公开(公告)日：2014-10-28

申请号：US13134225

申请日：2011-06-02

Applicant: Bum-soo Kim ,  Gui-young Lee ,  Jong-Min Kim ,  Ji-hyun In ,  Je-sung Kim ,  Sam-hyuk Noh ,  Sang-Iyul Min ,  Dong-hee Lee ,  Jae-yong Jeong ,  Yoo-kun Cho ,  Jong-moo Choi

Inventor： Bum-soo Kim ,  Gui-young Lee ,  Jong-Min Kim ,  Ji-hyun In ,  Je-sung Kim ,  Sam-hyuk Noh ,  Sang-Iyul Min ,  Dong-hee Lee ,  Jae-yong Jeong ,  Yoo-kun Cho ,  Jong-moo Choi

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/7203

Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.

Abstract translation: 提供闪存管理方法。 根据该方法，当向预先写入数据的页面写入预定数据的请求时，将预定数据写入对应于包含页面的数据块的日志块。 当接收到将预定数据再次写入页面的请求时，将预定数据写入日志块中的空闲空闲页面。 即使请求连续写入同一页面，管理方法也可以在一个日志块中进行处理，从而提高闪存资源的使用效率。

公开(公告)号：US08180976B2

公开(公告)日：2012-05-15

申请号：US10982560

申请日：2004-11-05

Applicant: Jae-Yong Jeong ,  Heung-soo Lim

Inventor： Jae-Yong Jeong ,  Heung-soo Lim

IPC: G06F12/00

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A nonvolatile memory device includes a memory cell array, a data scanning unit, and a program unit. The memory cell array includes a plurality of memory cells, where each of the memory cells is programmable to store data have a first logic value or a second logic value. The data scanning unit is configured to search among a plurality of data to be programmed in the memory cells to identify data having the second logic value. The program unit is configured to group the identified data having the second logic value, and to program at least a portion of the group of identified data at a same time into the memory cells.

Abstract translation: 非易失性存储器件包括存储单元阵列，数据扫描单元和程序单元。 存储单元阵列包括多个存储单元，其中每个存储器单元可编程以存储数据具有第一逻辑值或第二逻辑值。 数据扫描单元被配置为在存储器单元中要编程的多个数据之间搜索以识别具有第二逻辑值的数据。 程序单元被配置为对具有第二逻辑值的识别数据进行分组，并且将同一组的识别数据的至少一部分同时编程到存储器单元中。

公开(公告)号：US20110110164A1

公开(公告)日：2011-05-12

申请号：US12912001

申请日：2010-10-26

Applicant: Jae-Yong JEONG

Inventor： Jae-Yong JEONG

IPC: G11C5/00 ,  G11C16/06 ,  H03L5/00 ,  G11C29/00

CPC classification number: G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/44 ,  G11C2029/4402

Abstract: A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.

Abstract translation: 修剪电路包括修剪码存储单元，全局锁存单元和本地锁存单元。 修剪码存储单元存储多个修剪码，并响应于地址信号输出感测码。 全局锁存单元锁存校准代码或检测代码以产生全局输出信号。 通过对感测代码执行校准来生成校准代码。 本地锁存单元响应于地址信号反复锁存全局输出信号以产生多个修整输出信号。

公开(公告)号：US20100226172A1

公开(公告)日：2010-09-09

申请号：US12712769

申请日：2010-02-25

Applicant: In-Mo Kim ,  Jae-Yong Jeong

Inventor： In-Mo Kim ,  Jae-Yong Jeong

IPC: G11C16/04

CPC classification number: G11C16/34 ,  G11C11/5642 ,  G11C16/32

Abstract: A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address.

Abstract translation: 一种基于地址的选择位的逻辑电平读取非易失性存储器件中的数据的方法，确定读取与基于地址对应的一个多级存储器单元中存储的数据的第一和第二位的顺序 在选择位的逻辑电平上，根据确定的读数顺序来感测和输出数据的第一和第二位。 在非易失性存储器件中读取数据的方法以及在非易失性存储器件中输入和输出数据的方法可以通过选择读取多重存储器中存储的数据的第一和第二位的顺序来减少初始读取时间 级存储单元，并根据开始地址按顺序读取数据。

公开(公告)号：US20100023817A1

公开(公告)日：2010-01-28

申请号：US12499977

申请日：2009-07-09

Applicant: Jae-Woo PARK ,  Jae-Yong JEONG

Inventor： Jae-Woo PARK ,  Jae-Yong JEONG

IPC: G11C29/04 ,  G06F11/22

CPC classification number: G11C29/08 ,  G11C16/04 ,  G11C2029/0401 ,  G11C2029/0405 ,  G11C2029/0409

Abstract: A test system includes a memory device having a data I/O circuit connected to a data write-in path and a data read-out path. During test mode, the data I/O circuit retains a copy of test pattern data received in the I/O circuit via the data write-in path as output test data before the test pattern data is stored in a memory cell array as write data. The test system also includes a test device generating the test pattern data, receiving the output test data from the memory device, comparing the output test data with the test pattern data, and generating an error detection signal on the basis of the comparison. The error detection signal indicates the presence or absence of a defect in the data write-in or read-out path.

Abstract translation: 测试系统包括具有连接到数据写入路径和数据读出路径的数据I / O电路的存储器设备。 在测试模式期间，数据I / O电路通过数据写入路径保留在I / O电路中接收的测试图形数据的副本作为测试图形数据作为输出测试数据存储在存储单元阵列中作为写入数据 。 测试系统还包括产生测试图案数据的测试设备，从存储设备接收输出测试数据，将输出测试数据与测试模式数据进行比较，并且基于比较生成错误检测信号。 错误检测信号表示数据写入或读出路径中存在或不存在缺陷。

公开(公告)号：US20090055579A1

公开(公告)日：2009-02-26

申请号：US12230142

申请日：2008-08-25

Applicant: June-hong Park ,  Jae-yong Jeong ,  Chi-weon Yoon

Inventor： June-hong Park ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C11/5628 ,  G11C16/10 ,  G11C2216/14

Abstract: Provided is a semiconductor memory device for simultaneously programming a plurality of banks. The semiconductor memory device includes: a memory cell array comprising a plurality of banks; a plurality of data buffers storing a plurality of pieces of program data to be programmed in the corresponding banks; and a plurality of scan latches configured to scan the plurality of program data transmitted from the corresponding data buffers, and configured to generate 1st through n−1th sub program data, n being a natural number greater than 2.

Abstract translation: 提供了一种用于同时编程多个存储体的半导体存储器件。 半导体存储器件包括：包括多个存储体的存储单元阵列; 多个数据缓冲器，存储要在对应的存储体中编程的多个程序数据; 以及多个扫描锁存器，被配置为扫描从相应的数据缓冲器发送的多个节目数据，并且被配置为生成第1到第n个第1个子节目数据，n是大于2的自然数。

公开(公告)号：US07457165B2

公开(公告)日：2008-11-25

申请号：US11855531

申请日：2007-09-14

Applicant: Jae-Yong Jeong ,  Heung-Soo Lim

Inventor： Jae-Yong Jeong ,  Heung-Soo Lim

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/24

Abstract: Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.

Abstract translation: 公开了一种非易失性存储器件及其编程方法。 该方法包括在多个程序循环期间将字线电压，位线电压和体电压施加到存储器单元。 在当前程序循环期间位线电压下降到低于第一预定检测电压或体电压变得高于第二预定检测电压的情况下，在当前编程环路中使用相同的字线电压，并在下一个程序循环 当前程序循环。 否则，在下一个编程循环之前，字线电压增加预定量。

公开(公告)号：US07420852B2

公开(公告)日：2008-09-02

申请号：US11265279

申请日：2005-11-03

Applicant: Jae-Yong Jeong ,  Young-Ho Lim

Inventor： Jae-Yong Jeong ,  Young-Ho Lim

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/12

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and second program voltages thereto. In cases where the second program voltage rises above a predetermined detection voltage, the first program voltage is prevented from being supplied to the memory cell until the second program voltage falls below the detection voltage.

Abstract translation: 公开了一种非易失性存储器件及其编程方法。 非易失性存储器件包括通过向其提供第一和第二编程电压而被编程的多个存储单元。 在第二编程电压升高到高于预定检测电压的情况下，防止第一编程电压被提供给存储单元，直到第二编程电压下降到检测电压以下。

公开(公告)号：US20080068885A1

公开(公告)日：2008-03-20

申请号：US11946228

申请日：2007-11-28

Applicant: Jae-Phil KONG ,  Jae-Yong JEONG

Inventor： Jae-Phil KONG ,  Jae-Yong JEONG

IPC: G11C16/10

CPC classification number: G11C11/5628

Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.

Abstract translation: 一种在多级闪速存储器件中对所选单元进行编程的方法包括：确定是否编程所选存储单元的高位或低位，检测存储在所选存储单元中的两位数据的当前逻辑状态， 确定上位或下位的目标逻辑状态，产生用于将上位或下位编程为目标逻辑状态的编程电压和验证电压，以及将编程电压和验证电压施加到连接到所选择的字线的字线 记忆单元