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    STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING
    21.
    发明申请
    STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING 有权
    双嵌入式外延半导体加工中的应力优化

    公开(公告)号：US20100197093A1

    公开(公告)日：2010-08-05

    申请号：US12366356

    申请日：2009-02-05

    Applicant: Jong Ho Yang ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry Utomo

    Inventor： Jong Ho Yang ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry Utomo

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    Abstract: A method of manufacturing dual embedded epitaxially grown semiconductor transistors is provided, the method including depositing a first elongated oxide spacer over first and second transistors of different types, depositing a first elongated nitride spacer on the first oxide spacer, depositing a first photoresist block on the nitride spacer above the first transistor, etching the first nitride spacer above the second transistor, implanting a first halo around the second transistor, etching a first recess in an outer portion of the first halo, stripping the first photoresist above the first transistor, forming a first epitaxially grown semiconductor material in the first recess, implanting a first extension in a top portion of the first material, depositing an elongated blocking oxide over the first and second transistors and first extension, depositing a second photoresist block on the blocking oxide above the second transistor and first extension, etching the blocking oxide and first nitride spacer above the first transistor, implanting a second halo around the first transistor, etching a second recess in an outer portion of the second halo, stripping the second photoresist above the second transistor, forming a second epitaxially grown semiconductor material in the second recess, implanting a second extension in a top portion of the second material, etching the blocking oxide above the second transistor, etching nitride caps from the first and second transistors, depositing a second elongated oxide spacer on the first and second transistors, depositing a second elongated nitride spacer on the second oxide spacer, etching the second nitride spacer to leave nitride sidewalls around gates of the first and second transistors, and implanting deep sources and drains in the first and second transistors.

    Abstract translation: 提供了一种制造双嵌入式外延生长半导体晶体管的方法，所述方法包括在不同类型的第一和第二晶体管上沉积第一细长氧化物间隔物，在第一氧化物间隔物上沉积第一细长氮化物间隔物， 在所述第一晶体管上方蚀刻所述第一氮化物间隔物，在所述第二晶体管的上方蚀刻所述第一氮化物间隔区，在所述第二晶体管周围注入第一卤素，蚀刻所述第一卤素的外部部分中的第一凹陷， 在所述第一凹槽中的第一外延生长的半导体材料，在所述第一材料的顶部中注入第一延伸部，在所述第一和第二晶体管上沉积细长的阻塞氧化物，并且在所述第一和第二晶体管上沉积第一光致抗蚀剂阻挡层， 晶体管和第一延伸，首先蚀刻阻挡氧化物 在所述第一晶体管上方注入氮化物间隔物，在所述第一晶体管的周围注入第二卤素，蚀刻所述第二卤素的外部部分中的第二凹槽，在所述第二晶体管上剥离所述第二光致抗蚀剂，在所述第二凹槽中形成第二外延生长的半导体材料， 在第二材料的顶部注入第二延伸部分，蚀刻第二晶体管上方的阻挡氧化物，蚀刻来自第一和第二晶体管的氮化物盖，在第一和第二晶体管上沉积第二细长氧化物间隔物，沉积第二细长氮化物 隔离第二氧化物间隔物，蚀刻第二氮化物间隔物以在第一和第二晶体管的栅极周围留下氮化物侧壁，以及在第一和第二晶体管中注入深源和漏极。

    METAL GATE TRANSISTORS
    22.
    发明申请
    METAL GATE TRANSISTORS 审中-公开
    金属栅极晶体管

    公开(公告)号：US20100102393A1

    公开(公告)日：2010-04-29

    申请号：US12260095

    申请日：2008-10-29

    Applicant: James Yong Meng LEE ,  Jin-Ping HAN ,  Voon-Yew THEAN

    Inventor： James Yong Meng LEE ,  Jin-Ping HAN ,  Voon-Yew THEAN

    IPC: H01L27/092 ,  H01L21/4763

    CPC classification number: H01L21/823807 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor.

    Abstract translation: 公开了一种包括具有第一和第二有源区的衬底的集成电路。 第一类型的第一晶体管和第二类型的第二晶体管分别设置在第一和第二有源区中。 每个晶体管包括在栅极介电层上方具有金属栅电极的栅极堆叠。 提供了接触第一和第二晶体管的第一和第二栅极介电层的第一和第二栅极阈值电压调节（GTVA）层。 第一GTVA层调谐第一晶体管的栅极阈值电压。 第二晶体管的沟道包括用于调谐第二晶体管的栅极阈值电压的掺杂剂。

    Semiconductor Fabrication Process Including An SiGe Rework Method
    23.
    发明申请
    Semiconductor Fabrication Process Including An SiGe Rework Method 有权
    包括SiGe返工方法的半导体制造工艺

    公开(公告)号：US20100009502A1

    公开(公告)日：2010-01-14

    申请号：US12172756

    申请日：2008-07-14

    Applicant: Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

    Inventor： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

    IPC: H01L21/336

    CPC classification number: H01L29/1054 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

    Abstract translation: 一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。 将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。 进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

    Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
    29.
    发明申请
    Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same 有权
    具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法

    公开(公告)号：US20080119019A1

    公开(公告)日：2008-05-22

    申请号：US11602117

    申请日：2006-11-20

    Applicant: Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

    Inventor： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

    IPC: H01L21/8234

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

    Abstract translation: 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

    Method for fabricating a semiconductor device with a high-K dielectric
    30.
    发明申请
    Method for fabricating a semiconductor device with a high-K dielectric 审中-公开
    制造具有高K电介质的半导体器件的方法

    公开(公告)号：US20070190795A1

    公开(公告)日：2007-08-16

    申请号：US11352565

    申请日：2006-02-13

    Applicant: Haoren Zhuang ,  Jiang Yan ,  Jin-Ping Han ,  Jingyu Lian ,  Alois Gutmann

    Inventor： Haoren Zhuang ,  Jiang Yan ,  Jin-Ping Han ,  Jingyu Lian ,  Alois Gutmann

    IPC: H01L21/302

    CPC classification number: H01L21/0206 ,  H01L21/28123 ,  H01L29/513 ,  H01L29/517

    Abstract: Method for fabricating semiconductor devices with high-K materials without the presence of undesired formations of the high-K material. A preferred embodiment comprises forming a layer of material over a layer of a high-K material, etching the layer of material to expose a portion of the high-K material, performing a CDE (Chemical Downstream Etch) to remove any residual material formed during the etching, and etching the layer of the high-K material into alignment with remaining portions of the layer of material. The removal of the residual material results in a predictable trimming of the high-K material so that the semiconductor device has predictable and consistent performance, which is not possible if the high-K material has unpredictable dimensions.

    Abstract translation: 用于制造具有高K材料的半导体器件的方法，而不存在不需要的高K材料的形成。 优选的实施方案包括在高K材料层上形成一层材料，蚀刻该材料层以暴露一部分高K材料，进行CDE（化学下游蚀刻）去除在 蚀刻和蚀刻高K材料层与材料层的剩余部分对准。 剩余材料的去除导致高K材料的可预测的修整，使得半导体器件具有可预测和一致的性能，如果高K材料具有不可预测的尺寸，则这是不可能的。

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