公开(公告)号：US20120239866A1

公开(公告)日：2012-09-20

申请号：US13486387

申请日：2012-06-01

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G06F12/02

CPC分类号： G06F11/1068 ,  G11C16/10 ,  G11C16/26

摘要： The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer.

摘要翻译： 本公开是在页面复制操作期间具有错误检查和校正功能的NAND闪存。 NAND闪存能够禁止从源页面将错误位转录到重复页面。 本发明的闪速存储器的实施例包括用于校正存储在页缓冲器中的源数据的位错误的校正电路，配置成将源数据提供给校正电路并向校页电路提供校正数据的电路，以及配置 将源数据复制到页面缓冲器，并将校正数据存储在页面缓冲器的另一页中。

公开(公告)号：US20110299332A1

公开(公告)日：2011-12-08

申请号：US13209500

申请日：2011-08-15

申请人： Pyung-Moon ZHANG ,  Jin-Yub LEE

发明人： Pyung-Moon ZHANG ,  Jin-Yub LEE

IPC分类号： G11C16/10

CPC分类号： G01R31/3004 ,  G11C29/02 ,  G11C29/021 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56

摘要： Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result.

摘要翻译： 提供了一种测试系统和相关的高电压测量方法。 该方法包括：经由共享信道将外部电压信号施加到多个DUT中的一个或多个，将外部电压信号与由一个或多个DUT内部产生的高电压信号进行比较并产生相应的比较结果， 根据比较结果对各高压信号进行电压电平。

公开(公告)号：US20110205797A1

公开(公告)日：2011-08-25

申请号：US13008441

申请日：2011-01-18

申请人： Chan Ho KIM ,  Dong Kyu YOUN ,  Sang Won HWANG ,  Jin Yub LEE

发明人： Chan Ho KIM ,  Dong Kyu YOUN ,  Sang Won HWANG ,  Jin Yub LEE

IPC分类号： G11C16/08

CPC分类号： G11C8/12 ,  G11C16/0483 ,  G11C16/08

摘要： A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

摘要翻译： 非易失性存储器件包括第一垫，第二垫，第三垫，第一地址解码器，第二地址解码器和第三地址解码器。 第一垫包括第一存储块，第二垫包括第二存储块，第三块包括第三存储块。 第一地址解码器根据第一偶数地址选择第一存储块之一，第二地址解码器根据第二偶数地址或第一奇数地址选择第二存储块之一，并且第三地址解码器选择 第三存储器块根据第二奇数地址。

公开(公告)号：US07990129B2

公开(公告)日：2011-08-02

申请号：US12476565

申请日：2009-06-02

申请人： Joon Young Kwak ,  Yoon-Hee Choi ,  Jin-Yub Lee ,  You-Sang Lee ,  Bo-Geun Kim

发明人： Joon Young Kwak ,  Yoon-Hee Choi ,  Jin-Yub Lee ,  You-Sang Lee ,  Bo-Geun Kim

IPC分类号： G05F3/16

CPC分类号： G05F3/08

摘要： A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage.

摘要翻译： 参考电压产生电路提供稳定的参考电压并且包括： 提供时钟信号的时钟发生器，响应于时钟信号提供泵浦电压的高电压发生器，通过从所述泵浦电压去除电压纹波提供静态电压的纹波消除器以及提供参考电压的参考电压发生器。

公开(公告)号：US07839717B2

公开(公告)日：2010-11-23

申请号：US12235812

申请日：2008-09-23

申请人： Jin-wook Lee ,  Jin-yub Lee

发明人： Jin-wook Lee ,  Jin-yub Lee

IPC分类号： G11C8/18

CPC分类号： G11C5/14

摘要： A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode.

摘要翻译： 半导体存储器件包括：存储数据的单元核心，多个外围电路部件，共同地向单元核心驱动数据，并且在上电时的初始化处理期间以输出信号状态提供默认状态;以及初始化电路 检测半导体存储器件的待机操作模式，并且在检测到多个外围电路组件的待机模式控制操作时提供默认状态作为待机模式期间的信号状态。

公开(公告)号：US07692977B2

公开(公告)日：2010-04-06

申请号：US11837207

申请日：2007-08-10

申请人： Jin-Kook Kim ,  Jin-Yub Lee

发明人： Jin-Kook Kim ,  Jin-Yub Lee

IPC分类号： G11C5/14

CPC分类号： G11C16/0483 ,  G11C16/3454

摘要： High voltage generator circuits and methods for operating non-volatile semiconductor memory devices are provided for use with non-volatile memory such as FLASH memory devices, to selectively generate different types of control voltages for various operating modes of non-volatile memory devices.

摘要翻译： 提供用于操作非易失性半导体存储器件的高电压发生器电路和方法用于诸如闪速存储器件的非易失性存储器，以选择性地为非易失性存储器件的各种操作模式生成不同类型的控制电压。

公开(公告)号：US07646639B2

公开(公告)日：2010-01-12

申请号：US11844514

申请日：2007-08-24

申请人： Jin-wook Lee ,  Jin-Yub Lee

发明人： Jin-wook Lee ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： Provided are a circuit and method for generating a program voltage, and a non-volatile memory device using the same. The circuit, which generates a program voltage for programming a memory cell of a semiconductor memory device, includes a program voltage controller and a voltage generating unit. The program voltage controller generates a program voltage control signal according to program/erase operations information. The voltage controller generates a program voltage in response to the program voltage control signal.

摘要翻译： 提供了用于产生编程电压的电路和方法，以及使用其的非易失性存储器件。 产生用于对半导体存储器件的存储单元进行编程的编程电压的电路包括编程电压控制器和电压产生单元。 程序电压控制器根据编程/擦除操作信息产生编程电压控制信号。 电压控制器响应于编程电压控制信号产生编程电压。

公开(公告)号：US07558114B2

公开(公告)日：2009-07-07

申请号：US11454481

申请日：2006-06-16

申请人： Jin-Wook Lee ,  Jin-Yub Lee

发明人： Jin-Wook Lee ,  Jin-Yub Lee

IPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/26 ,  G11C16/3427

摘要： A flash memory device includes a memory cell array having a first region and a second region that include memory cells arranged in a plurality of rows and columns; an address storage circuit adapted to store address information for defining the second region; a row decoder circuit adapted to select one of the first and second regions in response to an external address; a voltage generating circuit adapted to generate a read voltage to be provided to a row of the selected region by the row decoder circuit during a read operation; a detecting circuit adapted to detect whether the selected region is included in the second region on the basis of address information and external address information that are stored in the address storage circuit; and a control logic adapted to control the voltage generating circuit in response to an output of the detecting circuit during the read operation. The control logic controls the voltage generating circuit so that a read voltage provided to the row of the second region is lower than a read voltage provided to a row of the first region.

摘要翻译： 闪速存储器件包括具有第一区域和第二区域的存储单元阵列，所述第二区域包括排列成多行和列的存储单元; 地址存储电路，适于存储用于定义第二区域的地址信息; 行解码器电路，其适于响应于外部地址来选择所述第一和第二区域中的一个; 电压发生电路，其适于在读取操作期间由行解码器电路产生要提供给所选区域的行的读取电压; 检测电路，其适于基于存储在所述地址存储电路中的地址信息和外部地址信息来检测所述选择区域是否包括在所述第二区域中; 以及控制逻辑，适于在读取操作期间响应于检测电路的输出来控制电压产生电路。 控制逻辑控制电压产生电路，使得提供给第二区域的行的读取电压低于提供给第一区域的行的读取电压。

公开(公告)号：US20090052252A1

公开(公告)日：2009-02-26

申请号：US12254205

申请日：2008-10-20

申请人： Hyung-seok Kang ,  Eui-gyu Han ,  Gyeong-soo Han ,  Jin-yub Lee ,  Hoo-sung Kim

发明人： Hyung-seok Kang ,  Eui-gyu Han ,  Gyeong-soo Han ,  Jin-yub Lee ,  Hoo-sung Kim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

摘要翻译： 提供了一种提高闪存阵列的读取干扰特性的方法。 根据该方法，在具有串联选择晶体管，多个存储单元和接地选择晶体管的至少一个单元串的闪速存储器阵列中，将第一读取电压施加到连接的串选择线 到串选择晶体管的栅极和连接到接地选择晶体管的栅极的接地选择线。 将接地电压施加到从存储单元中选择的存储单元的字线。 第二读取电压被施加到与串选择晶体管和地选择晶体管相邻的未被选择的存储单元中的存储单元的字线。 然后，将第一读取电压施加到未被选择的其他存储单元。 第二读取电压低于第一读取电压。

公开(公告)号：US20090019215A1

公开(公告)日：2009-01-15

申请号：US12216003

申请日：2008-06-27

申请人： Jin-Yub Lee ,  Sang-Won Hwang

发明人： Jin-Yub Lee ,  Sang-Won Hwang

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0893 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2245

摘要： Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time.

摘要翻译： 用于从半导体器件读取数据的方法和装置，其中t R是读取操作时间，tT是缓冲器传送时间，tH是主机传送时间，其中tR，tT和tH中的至少两个可以重叠以减少 总转会时间。