公开(公告)号：US20100290263A1

公开(公告)日：2010-11-18

申请号：US12495269

申请日：2009-06-30

申请人： Je-Yoon Kim ,  Jong-Chern Lee

发明人： Je-Yoon Kim ,  Jong-Chern Lee

IPC分类号： G11C19/00 ,  G11C7/00

CPC分类号： G11C19/00

摘要： A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the plurality of the shift stages are configured to sequentially shift the read signals for a period corresponding to burst setting information.

摘要翻译： 用于控制读周期的电路包括被配置为依次移位读信号的多个移位级; 以及激活单元，被配置为通过对所述多个移位级的输出信号执行逻辑运算来激活表示读取周期的读取周期信号，其中所述多个移位级被配置为将所读取的信号顺序地移位一段时间 对应于突发设置信息。

公开(公告)号：US08917569B2

公开(公告)日：2014-12-23

申请号：US13168241

申请日：2011-06-24

申请人： Min Seok Choi ,  Jong Chern Lee

发明人： Min Seok Choi ,  Jong Chern Lee

IPC分类号： G11C7/00 ,  G11C17/18

CPC分类号： G11C29/025 ,  G11C29/802 ,  G11C2029/4402

摘要： A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals.

摘要翻译： 半导体装置包括信号传输块和信号接收块。 信号传输块设置在第一芯片中并且被配置为与传输控制信号同步地发送熔丝信息。 信号接收块分别设置在第一芯片和第二芯片中，并被配置为与接收控制信号同步地接收熔丝信息。

公开(公告)号：US08687439B2

公开(公告)日：2014-04-01

申请号：US13181956

申请日：2011-07-13

申请人： Jae Bum Ko ,  Jong Chern Lee

发明人： Jae Bum Ko ,  Jong Chern Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1063 ,  G11C5/14 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/12

摘要： A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips.

摘要翻译： 一种半导体存储装置，其具备：具有规定容量和结构的一个以上的半导体芯片; 以及信号电平控制单元，被配置为控制输入到所述一个或多个半导体芯片的外部信号的电平，以便实现使用所述一个或多个半导体芯片的各种容量和结构。

公开(公告)号：US20130234326A1

公开(公告)日：2013-09-12

申请号：US13604481

申请日：2012-09-05

申请人： Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

发明人： Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

IPC分类号： H01L23/00 ,  H01L21/82

CPC分类号： H01L23/562 ,  H01L21/82 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： A semiconductor apparatus comprises of a first semiconductor chip having a through silicon via (TSV) and a second semiconductor chip also having a TSV, wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip.

摘要翻译： 半导体装置包括具有贯通硅通孔（TSV）的第一半导体芯片和也具有TSV的第二半导体芯片，其中各个半导体芯片垂直堆叠并通过导电连接构件连接，而无需附加凸块 在导电连接部件和第二半导体芯片之间。

公开(公告)号：US08477545B2

公开(公告)日：2013-07-02

申请号：US12839297

申请日：2010-07-19

申请人： Sin Hyun Jin ,  Jong Chern Lee

发明人： Sin Hyun Jin ,  Jong Chern Lee

IPC分类号： G11C7/22 ,  G11C8/18

CPC分类号： G11C7/00

摘要： A semiconductor apparatus includes a plurality of stacked chips. At least two of the chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column command in one of the at least two chips substantially coincide with the generation timing in the other of the at least two of the plurality of chips.

摘要翻译： 半导体装置包括多个堆叠芯片。 至少两个芯片被配置为接收列命令并且基于列命令生成列控制信号。 基于至少两个芯片之一中的列命令产生的列控制信号的生成定时基本上与多个芯片中的至少两个芯片中的另一个中的另一个中的生成定时一致。

公开(公告)号：US08446197B2

公开(公告)日：2013-05-21

申请号：US12755949

申请日：2010-04-07

申请人： Seung-Joon Ahn ,  Jong-Chern Lee

发明人： Seung-Joon Ahn ,  Jong-Chern Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/0814 ,  H03L7/07

摘要： A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.

摘要翻译： 延迟锁定环包括延迟脉冲产生单元，编码单元和延迟线。 延迟脉冲产生单元被配置为产生具有一定宽度的延迟脉冲。 编码单元被配置为对延迟脉冲进行编码并输出代码值。 延迟线被配置为通过代码值来延迟输入时钟，并产生延迟的锁定时钟。 延迟脉冲在与第一周期（对应于输入时钟的整数倍）和第二周期（在某个复制延迟周期）之间的差值的第三周期内具有逻辑高电平状态。

公开(公告)号：US08331171B2

公开(公告)日：2012-12-11

申请号：US12843673

申请日：2010-07-26

申请人： Jae Il Kim ,  Jong Chern Lee

发明人： Jae Il Kim ,  Jong Chern Lee

IPC分类号： G11C7/10

CPC分类号： G11C7/10

摘要： A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

摘要翻译： 半导体存储装置包括：第一数据输入/输出线，被配置为从第一存储体传输数据; 第二数据输入/输出线，被配置为从所述第一存储体发送所述数据; 第一数据输出部，被配置为基于输入/输出模式对准并输出通过第一数据输入/输出线传输的数据; 以及第二数据输出部分，被配置为基于输入/输出模式和地址信号对准并输出通过第一输入/输出线或第二数据输入/输出线传输的数据。

公开(公告)号：US20120249229A1

公开(公告)日：2012-10-04

申请号：US13236970

申请日：2011-09-20

申请人： Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

发明人： Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

IPC分类号： H01L25/00

CPC分类号： G11C8/12

摘要： A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

摘要翻译： 半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号 以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

公开(公告)号：US08242822B2

公开(公告)日：2012-08-14

申请号：US13400967

申请日：2012-02-21

申请人： Seung-Joon Ahn ,  Jong-Chern Lee

发明人： Seung-Joon Ahn ,  Jong-Chern Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0816 ,  H03L7/0814

摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

公开(公告)号：US08233339B2

公开(公告)日：2012-07-31

申请号：US12875803

申请日：2010-09-03

申请人： Hyun-Su Yoon ,  Jong-Chern Lee ,  Seung-Joon Ahn

发明人： Hyun-Su Yoon ,  Jong-Chern Lee ,  Seung-Joon Ahn

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2272

摘要： A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.

摘要翻译： 半导体存储器件包括开环型延迟锁定环（DLL），其被配置为通过反映实际发生在数据路径中的第一延迟量和锁定时钟信号所需的第二延迟量来产生锁定的时钟信号 等待时间控制单元，被配置为根据与第一延迟量和等待时间信息相对应的等待时间码值来移位输入的命令，并输出移位的命令;以及附加延迟线，被配置为根据延迟代码值来延迟移位的命令 对应于第二延迟量，并且输出控制哪个操作定时的命令。