公开(公告)号：US07724230B2

公开(公告)日：2010-05-25

申请号：US11375035

申请日：2006-03-15

Applicant: Sun Young Kim ,  Chul Sang Jang ,  Jong Hoon Kim

Inventor： Sun Young Kim ,  Chul Sang Jang ,  Jong Hoon Kim

IPC: G09G3/36

CPC classification number: G09G3/2003 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2310/0218

Abstract: A driving circuit of a display device includes a timing controller for combining p first digital data signals (p being a positive integer greater than 1) corresponding to colors for displaying images to generate q second digital data signals and for supplying the q second digital data signals to first to qth data transmission lines (q being a positive integer smaller than p), and a plurality of data driver integrated circuits for processing the q second digital data signals from the timing controller to restore the p first digital data signals, converting the p restored digital data signals into analog data signals, and supplying the analog data signals to a display panel.

Abstract translation: 显示装置的驱动电路包括：时序控制器，用于组合对应于用于显示图像的颜色的p个第一数字数据信号（p是大于1的正整数）以产生q个第二数字数据信号，并用于提供q个第二数字数据信号 到第一至第q数据传输线（q是小于p的正整数）和多个数据驱动器集成电路，用于处理来自定时控制器的q个第二数字数据信号以恢复p个第一数字数据信号，转换p 将数字数据信号恢复为模拟数据信号，并将模拟数据信号提供给显示面板。

公开(公告)号：US07595258B2

公开(公告)日：2009-09-29

申请号：US11753544

申请日：2007-05-24

Applicant: Jong Hoon Kim

Inventor： Jong Hoon Kim

IPC: H01L21/00

CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10T428/24694 ,  H01L2924/00

Abstract: After a mother vernier pattern is formed in a scribe region of a semiconductor substrate, a child vernier pad is formed on the inner region of a mother vernier, and a child vernier is formed on the child vernier pad in order to obviate the step of the mother vernier. Thus, at the time of an exposure process for forming the child vernier, failure of the pattern due to the step can be prevented and alignment can be measured accurately.

Abstract translation: 在半导体衬底的划片区域中形成母游标图案之后，在母游标的内部区域上形成儿童游标垫，并且在儿童游标垫上形成儿童游标，以消除 母亲游侠 因此，在用于形成儿童游标的曝光处理时，可以防止由于台阶引起的图案的故障，并且可以准确地测量对准。

公开(公告)号：US20090224392A1

公开(公告)日：2009-09-10

申请号：US12261112

申请日：2008-10-30

Applicant: Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM

Inventor： Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/04

CPC classification number: H01L23/4334 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311

Abstract: A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

Abstract translation: 半导体封装包括具有上表面的半导体芯片，与上表面连接的侧表面，以及形成在上表面上的焊盘。 形成第一绝缘层图案以覆盖半导体芯片的上表面和侧表面并且暴露接合焊盘。 再分配线路放置在第一绝缘层图案上，并且包括第一再分配线部分和第二再分配线部分。 第一再分配线部分具有与接合焊盘连接的端部并且对应于半导体芯片的上表面，并且第二再分配线部分从第一再分配线部分延伸超过半导体芯片的侧表面 。 在半导体芯片上形成第二绝缘层图案，并且暴露出第一再分配线部分和第二再分配线部分的部分。

公开(公告)号：US07575992B2

公开(公告)日：2009-08-18

申请号：US11518351

申请日：2006-09-08

Applicant: Woo Yung Jung ,  Jong Hoon Kim

Inventor： Woo Yung Jung ,  Jong Hoon Kim

IPC: H01L21/44 ,  H01L21/76 ,  H01L21/4763

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L27/0207 ,  H01L27/11524 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908 ,  Y10S438/947

Abstract: A method of forming a micro pattern in a semiconductor device is disclosed. An oxide film mask is divided into a cell oxide film mask and a peri oxide film mask. Therefore, a connection between the cell and the peri region can be facilitated. A portion of a top surface of a first oxide film pattern between a region in which a word line will be formed and a region in which a select source line will be formed is removed. Accordingly, the space can be increased and program disturbance in the region in which the word line will be formed can be prevented. Furthermore, a pattern having a line of 50 nm and a space of 100 nm or a pattern having a line of 100 nm and a space of 50 nm, which exceeds the limitation of the ArF exposure equipment, can be formed using a pattern, which has a line of 100 nm and a space of 200 nm and therefore has a good process margin and a good critical dimension regularity.

Abstract translation: 公开了一种在半导体器件中形成微图案的方法。 将氧化物膜掩模分为电池氧化膜掩模和氧化膜掩模。 因此，可以促进电池和周边区域之间的连接。 去除在其中将形成字线的区域和将形成选择源极线的区域之间的第一氧化膜图案的顶表面的一部分被去除。 因此，可以增加空间，并且可以防止在其中将形成字线的区域中的程序干扰。 此外，可以使用图案形成具有50nm线和100nm的线的图案或超过ArF曝光设备的限制的具有100nm和50nm的线的图案，其中 具有100nm的线和200nm的空间，因此具有良好的工艺裕度和良好的临界尺寸规律性。

公开(公告)号：US07539035B2

公开(公告)日：2009-05-26

申请号：US11649266

申请日：2007-01-04

Applicant: Jae-jun Lee ,  Jong-hoon Kim ,  Kwang-soo Park

Inventor： Jae-jun Lee ,  Jong-hoon Kim ,  Kwang-soo Park

IPC: G11C11/00

CPC classification number: G06F13/1694

Abstract: A memory system is disclosed with first, second, and third connectors located on a system board, the third connector including pins connected to the pins of the first and second connectors through channels, and a memory controller connected to the pins of the third connector through channels. The memory system, as configured in a first memory capacity, comprises; dummy memory modules and a first memory module connected to the memory controller by installing the dummy memory modules in the first and second connectors and installing the first memory module in the third connector. The memory system, as alternately configured in a second memory capacity larger than the first memory capacity, comprises second memory modules connected to the memory controller by installing the second memory modules in only the first and second connectors.

Abstract translation: 公开了一种存储系统，其中位于系统板上的第一，第二和第三连接器，第三连接器包括通过通道连接到第一和第二连接器的引脚的引脚，以及连接到第三连接器的引脚的存储器控​​制器，通过 频道 如第一存储器容量中配置的存储器系统包括： 虚拟存储器模块和通过将虚拟存储器模块安装在第一和第二连接器中而连接到存储器控制器的第一存储器模块，并将第一存储器模块安装在第三连接器中。 交替地配置在大于第一存储器容量的第二存储器容量中的存储器系统包括通过仅将第二存储器模块安装在第一和第二连接器中而连接到存储器控制器的第二存储器模块。

公开(公告)号：US20090121336A1

公开(公告)日：2009-05-14

申请号：US11954027

申请日：2007-12-11

Applicant: Jong Hoon KIM

Inventor： Jong Hoon KIM

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A stacked semiconductor package provides an enhanced data storage capacity along with an improved data processing speed. The stacked semiconductor package includes a substrate having chip selection pads and a connection pad; a semiconductor chip module including a plurality of semiconductor chips including data bonding pads, a chip selection bonding pad, and data redistributions electrically connected with the data bonding pads and a data through electrode passing through the data bonding pad and connected with the data redistribution, the semiconductor chips being stacked so as to expose the chip selection bonding pad; and a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads.

Abstract translation: 堆叠的半导体封装提供增强的数据存储容量以及改进的数据处理速度。 堆叠的半导体封装包括具有芯片选择焊盘和连接焊盘的衬底; 包括多个半导体芯片的半导体芯片模块，包括数据接合焊盘，芯片选择焊盘和与数据焊盘电连接的数据再分配，以及通过数据焊盘并与数据重新分配连接的数据通孔， 堆叠半导体芯片以使芯片选择焊盘露出; 以及用于将芯片选择焊盘和芯片选择焊盘电连接的导线。

公开(公告)号：US20080318361A1

公开(公告)日：2008-12-25

申请号：US11777388

申请日：2007-07-13

Applicant: Kwon Whan HAN ,  Chang Jun PARK ,  Min Suk SUH ,  Seong Cheol KIM ,  Sung Min KIM ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM ,  Ha Na LEE

Inventor： Kwon Whan HAN ,  Chang Jun PARK ,  Min Suk SUH ,  Seong Cheol KIM ,  Sung Min KIM ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM ,  Ha Na LEE

IPC: H01L21/44 ,  H01L21/02

CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

Abstract: A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Abstract translation: 一种半导体封装的制造方法，其特征在于，在设置有所述接合焊盘的半导体芯片的焊盘的外侧的部分的外表面形成有槽， 在所述槽的侧壁上形成绝缘层; 在半导体芯片上形成金属层，以填充形成有绝缘层的槽; 蚀刻金属层以同时形成用于填充槽的通过硅通孔和用于连接通过硅通孔和接合焊盘的分布层; 以及去除所述半导体芯片的后表面，使得所述贯穿硅通孔的下表面从所述半导体芯片突出。

公开(公告)号：US20080180120A1

公开(公告)日：2008-07-31

申请号：US11959881

申请日：2007-12-19

Applicant: Jong-hoon KIM ,  Hyun-ae Lee ,  Jin-ho So ,  Kwang-soo Park

Inventor： Jong-hoon KIM ,  Hyun-ae Lee ,  Jin-ho So ,  Kwang-soo Park

IPC: G01R1/067

CPC classification number: G01R1/07342

Abstract: A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

Abstract translation: 用于将半导体器件连接到测试设备的探针卡包括其中形成电布线图案的印刷电路板（PCB），固定在PCB的上表面上以将测试设备连接到PCB的第一连接器，探针 连接到半导体器件的电极焊盘，以及柔性PCB（FPCB），以将PCB连接到探针。 因此，能够提高信号传递特性，能够降低测试费用，降低接地噪声。

公开(公告)号：US20080044505A1

公开(公告)日：2008-02-21

申请号：US11570331

申请日：2005-06-09

Applicant: Hyun-Su Bae ,  Moon-Kyu Kang ,  Jong-Hoon Kim ,  Jung-Wan Oh ,  Chong-Woon Cho ,  Chang-Sook Kim ,  Hwa-Jin Lee ,  Hwan-Suck Chung ,  Moo-Chang Hong ,  Min-Kyu Shin ,  Hong-Yeoul Kim ,  Hyun Choi ,  Eun Jung Ko ,  Chang-Jun An

Inventor： Hyun-Su Bae ,  Moon-Kyu Kang ,  Jong-Hoon Kim ,  Jung-Wan Oh ,  Chong-Woon Cho ,  Chang-Sook Kim ,  Hwa-Jin Lee ,  Hwan-Suck Chung ,  Moo-Chang Hong ,  Min-Kyu Shin ,  Hong-Yeoul Kim ,  Hyun Choi ,  Eun Jung Ko ,  Chang-Jun An

IPC: A61K36/185 ,  A61P9/10

CPC classification number: A23G4/068 ,  A23G4/12 ,  A23G9/36 ,  A23G9/42 ,  A23L2/52 ,  A23L33/105 ,  A23V2002/00 ,  A61K36/62 ,  A23V2200/326 ,  A23V2250/21

Abstract: The present invention relates to an Nelumbinis semen extract having the effect of preventing or treating ischemic heart disease, as well as a pharmaceutical composition and health food for the prevention or treatment of ischemic heart diseases, which contain the Nelumbinis semen extract. The inventive Nelumbinis semen extract and the pharmaceutical composition and health food containing the same have the effect of recovering the heart which fails to function properly by ischemic heart diseases. Accordingly, they will be useful for the prevention or treatment of ischemic heart diseases, such as angina and myocardial infarction.

Abstract translation: 本发明涉及具有预防或治疗缺血性心脏病的效果的奈罗卜尼精液提取物，以及含有奈尔滨精液提取物的用于预防或治疗缺血性心脏病的药物组合物和保健食品。 本发明的Nelumbinis精液提取物及其含有的药物组合物和保健食品具有恢复心脏不能由缺血性心脏病正常发挥作用的作用。 因此，它们可用于预防或治疗心绞痛和心肌梗塞等缺血性心脏病。

公开(公告)号：US20070205848A1

公开(公告)日：2007-09-06

申请号：US11649805

申请日：2007-01-05

Applicant: Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

Inventor： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

IPC: H01P5/12 ,  H03H7/38

CPC classification number: H03H7/38

Abstract: A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

Abstract translation: 终端电路连接到接收数据信号的输入缓冲器，并且包括连接到输入缓冲器以用于阻抗匹配的至少一个终端电阻器。 至少一个开关控制输入缓冲器与至少一个终端电阻器中相应的一个之间的连接。 控制信号发生器产生控制信号，用于通过控制至少一个开关中的每个开关来选择性地启用终端电路。 控制信号的输入周期小于或等于数据信号的输入周期。