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公开(公告)号：US20240140624A1
公开(公告)日：2024-05-02
申请号：US18406214
申请日：2024-01-08
Applicant: Ha Na LEE
Inventor： Ha Na LEE , Jong Jin LEE
CPC classification number: B64U20/80 , G05D1/86 , B64U2201/00
Abstract: A drone integrated control device that controls a drone by unifying respective components on one board includes a flight control unit including a plurality of sensors and configured to control a path and a flight attitude of the drone, a motor control unit configured to control a rotation speed of at least one motor mounted to perform movements and takeoffs of the drone, a communication unit configured to transmit and receive control signals input to and output from the respective components included in the drone integrated control device, and a power supply unit configured to supply power to the respective components included in the drone integrated control device to operate the respective components.
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2.发明授权Wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield and a method for fabricating the same 有权具有EMF屏蔽的热交换效率提高的晶片级芯片级封装及其制造方法公开(公告)号：US08338921B2
公开(公告)日：2012-12-25
申请号：US13289365
申请日：2011-11-04
Applicant: Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Sung Min Kim , Hyeong Seok Choi , Ha Na Lee , Tac Keun Oh , Sang Joon Lim
Inventor： Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Sung Min Kim , Hyeong Seok Choi , Ha Na Lee , Tac Keun Oh , Sang Joon Lim
CPC classification number: H01L21/486 , H01L21/561 , H01L23/3114 , H01L23/367 , H01L23/552 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/94 , H01L24/96 , H01L24/97 , H01L2224/02379 , H01L2224/0401 , H01L2224/12105 , H01L2224/16 , H01L2224/94 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/3025 , H01L2224/11 , H01L2224/03 , H01L2924/00
Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.
Abstract translation: 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。
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公开(公告)号：US07859102B2
公开(公告)日：2010-12-28
申请号：US12048304
申请日：2008-03-14
Applicant: Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Hyeong Seok Choi , Ha Na Lee
Inventor： Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Hyeong Seok Choi , Ha Na Lee
IPC: H01L23/36
CPC classification number: H01L25/0657 , H01L25/0652 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2924/00014 , H01L2224/05599
Abstract: A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.
Abstract translation: 堆叠的晶片级半导体封装模块包括半导体芯片模块，其包括具有矩形形状的第一和第二半导体芯片。 第一半导体芯片具有沿其下表面的第一短边设置的第一焊盘。 第二半导体芯片具有沿其下表面的第一短边设置的第二焊盘。 第一和第二半导体芯片被堆叠以便在叠置的第一和第二半导体芯片的一侧上露出第一焊盘和第二焊盘。 封装还包括具有面向第一焊盘的第一连接焊盘和面向第二焊盘的第二连接焊盘的衬底。 该包装还包括用于将第一垫连接到第一连接垫的第一连接构件和用于将第二垫连接到第二连接垫的第二连接构件。
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公开(公告)号：US20090197372A1
公开(公告)日：2009-08-06
申请号：US12345858
申请日：2008-12-30
Applicant: Kwon Whan HAN , Chang Jun PARK , Seong Cheol KIM , Sung Min KIM , Hyeong Seok CHOI , Ha Na LEE
Inventor： Kwon Whan HAN , Chang Jun PARK , Seong Cheol KIM , Sung Min KIM , Hyeong Seok CHOI , Ha Na LEE
IPC: H01L21/00
CPC classification number: H01L24/16 , H01L21/6835 , H01L23/3114 , H01L23/481 , H01L24/11 , H01L24/17 , H01L24/90 , H01L24/97 , H01L25/50 , H01L2221/68372 , H01L2224/05001 , H01L2224/05548 , H01L2224/13009 , H01L2224/13099 , H01L2224/90 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014
Abstract: Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.
Abstract translation: 制造晶片级堆叠封装包括对包括多个第一半导体芯片的晶片的下表面进行背面磨削的步骤。 支撑构件附接到后磨碎晶片的下表面。 一个或多个第二半导体芯片堆叠在背面研磨的晶片的相应的第一半导体芯片上。 形成第一贯通电极以电连接堆叠的第一半导体芯片和第二半导体芯片。 第三半导体芯片附着到堆叠的第二半导体芯片的最上面，第三半导体芯片具有与连接到第二贯通电极的第一贯通电极和再分配线电连接的第二贯通电极。 外部连接端子附接到第三半导体芯片的再分配线路。 第二半导体芯片和第三半导体芯片堆叠的晶片级的第一半导体芯片在芯片级被锯切以用于半导体封装。
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5.发明申请WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME 审中-公开具有电磁屏蔽效果的增强热交换效率的WAFER LEVEL CHIP SCALE包装及其制造方法公开(公告)号：US20090184414A1
公开(公告)日：2009-07-23
申请号：US12347020
申请日：2008-12-31
Applicant: Chang Jun PARK , Kwon Whan HAN , Seong Cheol KIM , Sung Min KIM , Hyeong Seok CHOI , Ha Na LEE , Tac Keun OH , Sang Joon LIM
Inventor： Chang Jun PARK , Kwon Whan HAN , Seong Cheol KIM , Sung Min KIM , Hyeong Seok CHOI , Ha Na LEE , Tac Keun OH , Sang Joon LIM
IPC: H01L23/04 , H01L23/12 , H01L21/00 , H01L23/482 , H01L21/98
CPC classification number: H01L21/486 , H01L21/561 , H01L23/3114 , H01L23/367 , H01L23/552 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/94 , H01L24/96 , H01L24/97 , H01L2224/02379 , H01L2224/0401 , H01L2224/12105 , H01L2224/16 , H01L2224/94 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/3025 , H01L2224/11 , H01L2224/03 , H01L2924/00
Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.
Abstract translation: 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。
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Patent Agency Ranking
6.发明授权Naphthalene diimide-Zn(II) complex having selectivity for pyrophosphate, preparation method thereof and detecting method of pyrophosphate using the same 有权对焦磷酸盐具有选择性的萘二酰亚胺-Zn（II）络合物及其制备方法和使用其的焦磷酸盐的检测方法公开(公告)号：US07563897B2
公开(公告)日：2009-07-21
申请号：US11968120
申请日：2007-12-31
Applicant: Ju Young Yoon , Ha Na Lee , Sook Kyung Kim
Inventor： Ju Young Yoon , Ha Na Lee , Sook Kyung Kim
CPC classification number: G01N33/84 , C07D471/06 , G01N2021/7786
Abstract: The present invention provides a novel fluorescent chemosensor including a naphthalene diimide-Zn(II) complex, which can efficiently recognize pyrophosphate (PPi) at pH 7.4. The fluorescent chemosensor exhibits a new kind of excimer fluorescence, which is selective for PPi in 100% aqueous solution. Further, since the naphthalene diimide-Zn(II) complex of the present invention does not couple with inorganic phosphate (Pi) or adenosine triphosphate (ATP) and has high selectivity for PPi, it can be usefully used to detect pyrophosphate (PPi), which serves to transfer signals and store energy in living organisms.
Abstract translation: 本发明提供了一种新颖的荧光化学传感器，其包括萘二酰亚胺-Zn（II）络合物，其可以有效地识别pH 7.4的焦磷酸盐（PPi）。 荧光化学传感器显示出新型的准分子荧光，其对于100％水溶液中的PPi是选择性的。 此外，由于本发明的萘二酰亚胺-Zn（II）配合物不与无机磷酸盐（Pi）或三磷酸腺苷（ATP）偶联，对PPi具有高选择性，因此可用于检测焦磷酸（PPi）， 其用于传递信号并将能量储存在活生物体中。
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7.发明申请NAPHTHALENE DIIMIDE-ZN(II) COMPLEX HAVING SELECTIVITY FOR PYROPHOSPHATE, PREPARATION METHOD THEREOF AND DETECTING METHOD OF PYROPHOSPHATE USING THE SAME 有权具有磷酸选择性的萘二甲酰基-D-二炔（II）复合物，其制备方法和使用其的磷酸酯的检测方法公开(公告)号：US20080261196A1
公开(公告)日：2008-10-23
申请号：US11968120
申请日：2007-12-31
Applicant: Ju Young Yoon , Ha Na Lee , Sook Kyung Kim
Inventor： Ju Young Yoon , Ha Na Lee , Sook Kyung Kim
IPC: C12Q1/00 , C07D401/14
CPC classification number: G01N33/84 , C07D471/06 , G01N2021/7786
Abstract: The present invention provides a novel fluorescent chemosensor including a naphthalene diimide-Zn(II) complex, which can efficiently recognize pyrophosphate (PPi) at pH 7.4. The fluorescent chemosensor exhibits a new kind of excimer fluorescence, which is selective for PPi in 100% aqueous solution. Further, since the naphthalene diimide-Zn(II) complex of the present invention does not couple with inorganic phosphate (Pi) or adenosine triphosphate (ATP) and has high selectivity for PPi, it can be usefully used to detect pyrophosphate (PPi), which serves to transfer signals and store energy in living organisms.
Abstract translation: 本发明提供了一种新颖的荧光化学传感器，其包括萘二酰亚胺-Zn（II）络合物，其可以有效地识别pH 7.4的焦磷酸盐（PPi）。 荧光化学传感器显示出新型的准分子荧光，其对于100％水溶液中的PPi是选择性的。 此外，由于本发明的萘二酰亚胺-Zn（II）配合物不与无机磷酸盐（Pi）或三磷酸腺苷（ATP）偶联，对PPi具有高选择性，因此可用于检测焦磷酸（PPi）， 其用于传递信号并将能量储存在活生物体中。
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10.发明授权Semiconductor chip with chip selection structure and stacked semiconductor package having the same 有权具有芯片选择结构的半导体芯片和具有相同的堆叠半导体封装公开(公告)号：US07898834B2
公开(公告)日：2011-03-01
申请号：US12059308
申请日：2008-03-31
Applicant: Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Ha Na Lee
Inventor： Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Ha Na Lee
IPC: G11C5/02
CPC classification number: H01L23/50 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/17 , H01L25/0657 , H01L2224/0235 , H01L2224/02375 , H01L2224/0401 , H01L2224/05001 , H01L2224/0554 , H01L2224/05552 , H01L2224/06051 , H01L2224/06165 , H01L2224/06167 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2924/0001 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/00012 , H01L2224/13099
Abstract: A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.
Abstract translation: 具有适合堆叠半导体芯片的芯片选择结构的半导体芯片包括半导体芯片体和芯片选择结构。 芯片选择结构包括设置在半导体芯片主体上的芯片选择焊盘，电连接到芯片选择焊盘的主通孔以及置于主通孔和芯片选择焊盘之间的副通孔。 可以通过抵消堆叠的半导体芯片来堆叠各自具有相同芯片选择结构的多个半导体芯片。
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