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    Magnetic random access memory device and method of forming the same
    22.
    发明授权
    Magnetic random access memory device and method of forming the same 有权
    磁性随机存取存储器件及其形成方法

    公开(公告)号：US07372090B2

    公开(公告)日：2008-05-13

    申请号：US11347280

    申请日：2006-02-06

    Applicant: Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

    Inventor： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

    Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

    Abstract translation: 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠 下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的 较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作， 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。

    Methods of Forming Magnetic Random Access Memory Devices Including Contact Plugs Between Magnetic Tunnel Junction Structures and Substrates
    23.
    发明申请
    Methods of Forming Magnetic Random Access Memory Devices Including Contact Plugs Between Magnetic Tunnel Junction Structures and Substrates 审中-公开
    在磁性隧道结结构和基板之间形成包括接触塞的磁性随机存取存储器件的方法

    公开(公告)号：US20070230242A1

    公开(公告)日：2007-10-04

    申请号：US11762319

    申请日：2007-06-13

    Applicant: Jang Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Young-Ki Ha ,  Kyung-Tae Nam

    Inventor： Jang Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Young-Ki Ha ,  Kyung-Tae Nam

    IPC: G11C11/02

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161

    Abstract: A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.

    Abstract translation: 磁性随机存取存储器件可以包括半导体衬底，磁性隧道结（MTJ）结构，接触插塞和数字线。 更具体地，MTJ结构可以在半导体衬底上，并且数字线可以与磁性隧道结结构相邻。 此外，接触插头可以在磁性隧道结结构和半导体衬底之间提供电连接，并且接触插塞可以在磁性隧道结结构和半导体衬底之间。 还讨论了相关方法。

    Magnetic Random Access Memory Devices Including Contact Plugs Between Magnetic Tunnel Junction Structures and Substrates and Related Methods
    24.
    发明申请
    Magnetic Random Access Memory Devices Including Contact Plugs Between Magnetic Tunnel Junction Structures and Substrates and Related Methods 审中-公开
    包括磁性隧道结结构和基板之间的接触插塞的磁性随机存取存储器件及相关方法

    公开(公告)号：US20070206411A1

    公开(公告)日：2007-09-06

    申请号：US11746810

    申请日：2007-05-10

    Applicant: Jang Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Young-Ki Ha ,  Kyung-Tae Nam

    Inventor： Jang Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Young-Ki Ha ,  Kyung-Tae Nam

    IPC: G11C11/14

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161

    Abstract: A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.

    Abstract translation: 磁性随机存取存储器件可以包括半导体衬底，磁性隧道结（MTJ）结构，接触插塞和数字线。 更具体地，MTJ结构可以在半导体衬底上，并且数字线可以与磁性隧道结结构相邻。 此外，接触插头可以在磁性隧道结结构和半导体衬底之间提供电连接，并且接触插塞可以在磁性隧道结结构和半导体衬底之间。 还讨论了相关方法。

    Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same
    25.
    发明授权
    Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same 有权
    具有氧化缓冲层的磁隧道结结构及其制造方法

    公开(公告)号：US07141438B2

    公开(公告)日：2006-11-28

    申请号：US10915872

    申请日：2004-08-10

    Applicant: Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Jun-Soo Bae ,  In-Gyu Baek

    Inventor： Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Jun-Soo Bae ,  In-Gyu Baek

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  H01L43/08

    Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

    Abstract translation: 提供了一种磁性隧道结结构及其制造方法。 磁性隧道结结构包括依次形成在下电极上的下电极，下磁层图案和隧道层图案。 磁隧道结结构还包括依次形成在隧道层图案的一部分上的上磁层图案，缓冲层图案和上电极。 上部磁性层图案的侧壁由氧化的上部磁性层包围，缓冲层图案的侧壁由氧化的缓冲层包围。 可以通过氧化缓冲层来防止磁性隧道结区域中上部磁性层图案和下部磁性层图案的消耗。

    Magnetic random access memory devices including contact plugs between magnetic tunnel junction structures and substrates and related methods
    27.
    发明申请
    Magnetic random access memory devices including contact plugs between magnetic tunnel junction structures and substrates and related methods 审中-公开
    磁性随机存取存储器件包括磁性隧道结结构和衬底之间的接触插塞以及相关方法

    公开(公告)号：US20060027846A1

    公开(公告)日：2006-02-09

    申请号：US11145478

    申请日：2005-06-03

    Applicant: Jang-Eun Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Young-Ki Ha ,  Kyung-Tae Nam

    Inventor： Jang-Eun Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Young-Ki Ha ,  Kyung-Tae Nam

    IPC: H01L29/94

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161

    Abstract: A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.

    Abstract translation: 磁性随机存取存储器件可以包括半导体衬底，磁性隧道结（MTJ）结构，接触插塞和数字线。 更具体地，MTJ结构可以在半导体衬底上，并且数字线可以与磁性隧道结结构相邻。 此外，接触插头可以在磁性隧道结结构和半导体衬底之间提供电连接，并且接触插塞可以在磁性隧道结结构和半导体衬底之间。 还讨论了相关方法。

    PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    29.
    发明申请
    PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    相变存储器件及其制造方法

    公开(公告)号：US20120273741A1

    公开(公告)日：2012-11-01

    申请号：US13443132

    申请日：2012-04-10

    Applicant: Kyu-Man HWANG ,  Jun-Soo BAE ,  Sung-Un KWON ,  Kwang-Ho PARK

    Inventor： Kyu-Man HWANG ,  Jun-Soo BAE ,  Sung-Un KWON ,  Kwang-Ho PARK

    IPC: H01L47/00 ,  H01L21/02

    CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1683

    Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.

    Abstract translation: 一种制造相变存储器件的方法包括：形成下电极层图案和覆盖下电极层图案的绝缘夹层，在绝缘中间层中形成第一开口以露出下电极层图案，在其上形成氧化层图案 通过部分地除去氧化物层和下部电极层图案，形成绝缘层，在第一开口的侧壁和下部电极的下方形成氧化物层图案，形成绝缘层，填充第一开口的剩余部分，通过湿蚀刻工艺去除氧化物层图案 以形成第二开口，并且在下电极上形成相变材料图案，使得相变材料图案填充第二开口。

    Variable resistance memory device and system thereof
    30.
    发明授权
    Variable resistance memory device and system thereof 有权
    可变电阻存储器件及其系统

    公开(公告)号：US08139432B2

    公开(公告)日：2012-03-20

    申请号：US12901168

    申请日：2010-10-08

    Applicant: Byung-gil Choi ,  Beak-hyung Cho ,  Jun-Soo Bae ,  Kwang-Jin Lee

    Inventor： Byung-gil Choi ,  Beak-hyung Cho ,  Jun-Soo Bae ,  Kwang-Jin Lee

    IPC: G11C7/04

    CPC classification number: G11C7/18 ,  G11C7/04 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2029/2602 ,  H01L27/24

    Abstract: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

    Abstract translation: 一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。

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