公开(公告)号：US20090160484A1

公开(公告)日：2009-06-25

申请号：US12004617

申请日：2007-12-21

Applicant: Kiyoshi Kase ,  May Len ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  May Len ,  Dzung T. Tran

IPC: H03K19/0175

CPC classification number: H03K19/018521

Abstract: Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

Abstract translation: 用于缓冲输入信号的方法和相应系统包括响应于输入信号低于较低阈值输出第一逻辑值。 响应于输入信号上升到较低阈值以上而输出第二逻辑值。 此后，维持第二逻辑值，直到输入超过较高阈值，然后低于较高阈值。 响应于输入信号低于较高阈值，第一逻辑值被输出并保持在第一逻辑值，直到输入低于低阈值，然后上升到低于下阈值。

公开(公告)号：US07358796B2

公开(公告)日：2008-04-15

申请号：US11530181

申请日：2006-09-08

Applicant: Kiyoshi Kase ,  May Len

Inventor： Kiyoshi Kase ,  May Len

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H03F3/45192 ,  H03F3/45632 ,  H03F2203/45352

Abstract: An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.

Abstract translation: 输入电压电路包括具有用于接收可变输入电压的控制电极的输入晶体管，具有耦合到形成第一节点的输入晶体管的电流电极的电流电极的电压检测晶体管，以及耦合到第二电流的电流源 形成第二节点的电压检测晶体管的电极。 输入电压电路还包括可变压降晶体管，其具有耦合到第一节点的第一电流电极，耦合到第二节点的控制电极和耦合到输出节点的第二电流电极，其中电压检测晶体管检测到 可变输入电压并向可变压降晶体管提供信号。 可变压降晶体管产生与可变输入电压的变化成比例的电压降，以确保输出节点处的输出基本恒定。

公开(公告)号：US20050146355A1

公开(公告)日：2005-07-07

申请号：US10747748

申请日：2003-12-29

Applicant: Kiyoshi Kase ,  May Len ,  Dzung Tran

Inventor： Kiyoshi Kase ,  May Len ,  Dzung Tran

IPC: H03K3/356 ,  H03K17/10 ,  H03K19/094

CPC classification number: H03K17/102 ,  H03K3/356008 ,  H03K3/356113

Abstract: A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.

Abstract translation: 具有不同阈值电压的交叉耦合反相器的电平移位器。 在上电期间，电平转换器的输出被拉到已知的电压状态。 在一些示例中，一个反相器包括附加的N沟道晶体管，其中由于附加晶体管，阈值电压大于另一个反相器的阈值电压。

公开(公告)号：US5905453A

公开(公告)日：1999-05-18

申请号：US905700

申请日：1997-08-04

Applicant: Kiyoshi Kase

Inventor： Kiyoshi Kase

IPC: H03M3/02

CPC classification number: H03M3/332 ,  H03M3/43 ,  H03M3/454 ,  H03M3/494

Abstract: A sigma delta modulator (10) for use in codec applications provides dynamic range adjustment and avoids asymmetrical signal clipping. The modulator (10) has a summing circuit that sums a plurality of inputs, one of which is a dither component. The dither is programmably modifiable to provide enhanced performance. The dither is provided by a pseudo random number generator (100). The pseudo random number generator (100) has an n-bit shift register (106) coupled to a last code detect (108) to detect the end of a pseudo random number sequence. At that time, a new preset code can be loaded (110) into the shift register (106) to provide different dither characteristics. This allows the pseudo random number generator (100) to programmably determine the percentage of ones and zeros to add to the output signal. The dither output can be inverted (104) to shift the dither up or down.

Abstract translation: 用于编解码器应用的Σ-Δ调制器（10）提供动态范围调整并避免不对称信号限幅。 调制器（10）具有对多个输入进行求和的求和电路，其中一个输入是抖动分量。 抖动可编程，以提供更好的性能。 抖动由伪随机数发生器（100）提供。 伪随机数发生器（100）具有耦合到最后代码检测（108）的n位移位寄存器（106），以检测伪随机数序列的结束。 此时，可以将新的预设代码加载到移位寄存器（106）中以提供不同的抖动特性。 这允许伪随机数发生器（100）可编程地确定添加到输出信号的1和0的百分比。 抖动输出可以反转（104）以将抖动向上或向下移动。

公开(公告)号：US5892381A

公开(公告)日：1999-04-06

申请号：US868335

申请日：1997-06-03

Applicant: Vladimir Koifman ,  Yachin Afek ,  Eliezer Sand ,  Kiyoshi Kase

Inventor： Vladimir Koifman ,  Yachin Afek ,  Eliezer Sand ,  Kiyoshi Kase

IPC: H03F1/00 ,  G05F1/46 ,  G05F3/16

CPC classification number: G05F1/468

Abstract: The rise time of a voltage Vo presented to a load, based on an input voltage Vi provided via an RC filter coupled to the load for removing higher frequency noise on Vo, is substantially reduced by providing a sensor circuit with differential inputs Vi, Vo. The sensor circuit drives a charger circuit coupled to a DC potential and the load so that rapid charging of C to Vo does not depend on R. As Vo approaches Vi, the sensor circuit deactivates the charger circuit to stop further charging and a latch coupled to the sensor circuit shuts off the sensor circuit to reduce power consumption while (Vo.about.Vi)>0. A current mirror buffer is desirably included between the sensor output and the latch for level shifting.

Abstract translation: 基于通过耦合到负载的用于消除Vo上的更高频率噪声的RC滤波器提供的输入电压Vi，提供给负载的电压Vo的上升时间通过向具有差分输入Vi，Vo的传感器电路提供而大大减少。 传感器电路驱动耦合到直流电位和负载的充电器电路，使得C至Vo的快速充电不依赖于R.当Vo接近Vi时，传感器电路使充电器电路停用以停止进一步的充电，并将锁存器耦合到 传感器电路关闭传感器电路，以减少功耗（Vo差分Vi）> 0。 理想地，传感器输出和锁存器之间包括电流镜缓冲器以进行电平转换。

公开(公告)号：US5231320A

公开(公告)日：1993-07-27

申请号：US947084

申请日：1992-09-18

Applicant: Kiyoshi Kase

Inventor： Kiyoshi Kase

IPC: H03K3/017 ,  H03K5/00 ,  H03K5/04 ,  H03K5/13

CPC classification number: H03K5/04 ,  H03K3/017 ,  H03K5/133 ,  H03K2005/00097 ,  H03K2005/0013 ,  H03K2005/00195

Abstract: A delay line having feedback from a control circuit at the output of the delay line controls the delay line duty cycle to within a specified range. The delay line comprises at least one delay unit having control inputs to each delay unit. The output of the delay line feeds to a low-pass filter (LPF). A voltage proportional to the duty cycle of the delay line output is generated within the LPF and fed to a differential amplifier. The differential amplifier is in turn coupled to the control inputs of each of the delay units. When the voltage signal from the LPF is high (duty cycle is high), the differential amplifier will generate a signal causing the fall time of the signal propagating through the delay line to increase and rise time to decrease. This will decrease the high cycle time at the output of the delay line. When the voltage signal from the LPF is low (duty cycle is low), the differential amplifier will generate a signal causing the fall time to decrease and the rise time to increase. This will increase the high cycle time at the output of the delay line.

Abstract translation: 在延迟线的输出处具有来自控制电路的反馈的延迟线将延迟线占空比控制在指定范围内。 延迟线包括至少一个具有到每个延迟单元的控制输入的延迟单元。 延迟线的输出馈送到低通滤波器（LPF）。 在LPF内产生与延迟线输出的占空比成比例的电压，并馈送到差分放大器。 差分放大器又耦合到每个延迟单元的控制输入端。 当来自LPF的电压信号为高电平（占空比为高）时，差分放大器将产生一个信号，导致信号通过延迟线传播的下降时间增加并且上升时间减少。 这将减少延迟线输出端的高周期时间。 当LPF的电压信号为低电平（占空比为低）时，差分放大器将产生一个信号，导致下降时间减少，上升时间增加。 这将延长延迟线输出端的高周期时间。

公开(公告)号：US5198780A

公开(公告)日：1993-03-30

申请号：US870750

申请日：1992-04-20

Applicant: Kiyoshi Kase

Inventor： Kiyoshi Kase

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03G1/007 ,  H03F3/45766

Abstract: A differential amplifier avoids gain fluctuations due to process differences and changes in temperature and allows adjustability of the gain and associated frequency characteristics to desired gain values. The amplifier comprises a pair of load transistors coupled to a pair of differential input transistors. A pair of biased current source transistors assure a constant current through the differential transistors, and a pair of bias transistors supply a constant bias to the source of the load transistors. The gain is varied by varying the voltage supplied to the gates of the two load transistors. The voltage supplied to the load transistors is varied by varying the current supplied through a second pair of bias transistors. A number of current source transistors coupled in parallel vary the voltage through the second pair of bias transistors.

Abstract translation: 差分放大器避免了由于工艺差异和温度变化引起的增益波动，并允许增益和相关频率特性对所需增益值的可调性。 放大器包括耦合到一对差分输入晶体管的一对负载晶体管。 一对偏置电流源晶体管确保通过差分晶体管的恒定电流，并且一对偏置晶体管向负载晶体管的源极提供恒定的偏置。 通过改变提供给两个负载晶体管的栅极的电压来改变增益。 通过改变通过第二对偏置晶体管提供的电流来改变提供给负载晶体管的电压。 并联耦合的多个电流源晶体管通过第二对偏置晶体管改变电压。

公开(公告)号：US07680231B2

公开(公告)日：2010-03-16

申请号：US11349874

申请日：2006-02-08

Applicant: John E. Angello ,  Satyavathi Akella ,  Kiyoshi Kase ,  May Len

Inventor： John E. Angello ,  Satyavathi Akella ,  Kiyoshi Kase ,  May Len

IPC: H04L25/38

CPC classification number: H04L25/38 ,  H04L7/0008

Abstract: An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.

Abstract translation: 一种自适应可变长度脉冲同步器，包括状态保持器电路，异步脉冲沿检测电路，数据同步电路和脉冲沿同步电路。 状态保持电路检测异步脉冲的前沿。 在状态保持电路检测到前沿之后，异步脉冲沿检测电路检测异步脉冲的后沿。 在检测到异步脉冲之后，异步脉冲沿检测电路还提供与时钟信号同步的脉冲。 数据同步电路锁存异步数据，并响应于同步脉冲提供同步数据。 在提供同步数据之后，脉冲沿同步提供同步就绪信号。 在一个实施例中，同步脉冲发生在时钟的连续上升沿之间，而响应于时钟的中间下降沿提供同步就绪信号。

公开(公告)号：US20090237164A1

公开(公告)日：2009-09-24

申请号：US12053754

申请日：2008-03-24

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03F3/45

CPC classification number: H03K17/04206 ,  H03K17/063

Abstract: A circuit includes first, second, and third inverters and first and second transistors. The first inverter has an input, an output, a first supply terminal, and a second supply terminal. The second inverter has an input, an output, a first supply terminal, and a second supply terminal. The first transistor has a first current electrode for receiving a first supply voltage, a control electrode coupled to the output of the first inverter, and a second current electrode coupled to the first supply terminals of both the first and second inverters. The second transistor has a first current electrode coupled to the second supply terminals of the first and second inverters, a control electrode coupled to the output of the first inverter, and a second current electrode for receiving a second supply voltage. The third inverter has an input coupled to the output of the second inverter, and an output coupled to the output of the first inverter.

Abstract translation: 电路包括第一，第二和第三反相器以及第一和第二晶体管。 第一逆变器具有输入端，输出端，第一供电端子和第二供电端子。 第二逆变器具有输入端，输出端，第一供电端子和第二供电端子。 第一晶体管具有用于接收第一电源电压的第一电流电极，耦合到第一反相器的输出的控制电极和耦合到第一和第二逆变器的第一电源端子的第二电流电极。 第二晶体管具有耦合到第一和第二反相器的第二电源端的第一电流电极，耦合到第一反相器的输出的控制电极和用于接收第二电源电压的第二电流电极。 第三反相器具有耦合到第二反相器的输出的输入端和耦合到第一反相器的输出的输出。

公开(公告)号：US20080068061A1

公开(公告)日：2008-03-20

申请号：US11532295

申请日：2006-09-15

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03H11/26

CPC classification number: H03H11/26

Abstract: A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

Abstract translation: 电路的性能可以基于诸如例如工艺，电压和/或温度的各种因素而变化。 在一个实施例中，电路包括接收输入信号的输入端子，延迟选择部分，其将输入信号延迟由性能变化指示器选择的延迟量;阻抗选择部分，其输出延迟的输入信号作为经补偿的延迟 信号，其中阻抗选择部分使用由性能变化指示器选择的驱动器阻抗量，以及输出端子，其输出经补偿的延迟信号。 电路还可以包括环形振荡器，频率计数器，其提供指示在参考频率的周期期间发生的环形振荡器的输出的上升沿的数量的计数值;以及解码器，其使用计数值 输出性能变化指标。