公开(公告)号：US20060134913A1

公开(公告)日：2006-06-22

申请号：US11338579

申请日：2006-01-23

Applicant: Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

Inventor： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

IPC: H01L21/44 ,  H01L21/302

CPC classification number: H01L21/28052 ,  H01L29/4933

Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

公开(公告)号：US20050020044A1

公开(公告)日：2005-01-27

申请号：US10683612

申请日：2003-10-10

Applicant: Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

Inventor： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

IPC: H01L21/28 ,  H01L21/4763 ,  H01L29/49

CPC classification number: H01L21/28052 ,  H01L29/4933

Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

Abstract translation: 一种半导体制造方法，该半导体器件具有堆叠栅极结构。 通过介电层与衬底绝缘的衬底上形成多晶硅层。 在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。 使用氮气和氢气对氮化钨层进行退火。 依次形成覆盖氮化钨层的钨层和覆盖层。

公开(公告)号：US09647133B2

公开(公告)日：2017-05-09

申请号：US15036662

申请日：2014-11-13

Applicant: Duy Vu Pham ,  Kuo Hui Su

Inventor： Duy Vu Pham ,  Kuo Hui Su

IPC: H01L29/04 ,  H01L29/786 ,  H01L29/417 ,  H01L29/45 ,  H01L21/02 ,  H01L23/31 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02271 ,  H01L23/3171 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78618

Abstract: The present invention relates to a novel thin film transistor (TFT) comprising a substrate (100) with a gate electrode layer (101) deposited and patterned thereon and a gate insulator layer (102) deposited on the gate electrode layer and the substrate, characterized in that the transistor further comprises (i) a carrier injection layer (103) arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer (104) deposited on the carrier injection layer, and (iii) a semiconductor layer (106), methods for the production of such novel TFTs, devices comprising such TFTs, and to the use of such TFTs.

公开(公告)号：US08772119B2

公开(公告)日：2014-07-08

申请号：US13236656

申请日：2011-09-20

Applicant: Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/336

CPC classification number: H01L29/66606 ,  H01L21/28044 ,  H01L29/66553 ,  H01L29/78

Abstract: A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.

Abstract translation: 提供晶体管的制造方法。 图案化的牺牲层形成在衬底上，其中图案化牺牲层包括暴露衬底的多个开口。 通过使用图案化牺牲层作为掩模，在衬底上进行掺杂工艺，从而在由开口暴露的衬底中形成掺杂源极区域和掺杂漏极区域。 执行选择性生长工艺以在掺杂源极区域和掺杂漏极区域上分别形成源极和漏极。 去除图案化牺牲层以暴露源极和漏极之间的衬底。 在源极和漏极之间的衬底上形成栅极。

公开(公告)号：US08754531B2

公开(公告)日：2014-06-17

申请号：US13419451

申请日：2012-03-14

Applicant: Yu-Shan Chiu ,  Kuo-Hui Su

Inventor： Yu-Shan Chiu ,  Kuo-Hui Su

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/13 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A through-silicon via (TSV) includes an insulation layer continuously lining a straight sidewall of a recessed via feature; a barrier layer continuously covering the insulation layer; a first portion of a non-continuous seed layer disposed at one end of the recessed via feature; a non-continuous dielectric layer partially covering the straight sidewall of the recessed via feature; and a conductive layer filling the recessed via feature.

Abstract translation: 贯穿硅通孔（TSV）包括连续地衬在凹陷通孔特征的直侧壁上的绝缘层; 连续地覆盖绝缘层的阻挡层; 设置在凹陷通孔特征的一端的非连续种子层的第一部分; 部分地覆盖凹陷通孔特征的直侧壁的非连续介电层; 以及填充凹陷通孔特征的导电层。

公开(公告)号：US20140001633A1

公开(公告)日：2014-01-02

申请号：US13535217

申请日：2012-06-27

Applicant: Chi-Wen Huang ,  Kuo-Hui Su

Inventor： Chi-Wen Huang ,  Kuo-Hui Su

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/31133 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/76834 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a copper interconnect structure is disclosed. A substrate having a conductive region is provided. An insulating layer with a via opening is formed on the substrate. The via opening exposes the conductive region. A copper layer is formed on the first insulating layer and fills the via opening by sequentially performing deposition and reflowing processes. A masking layer is formed on the copper layer to cover the via opening. The copper layer uncovered by the masking layer is anisotropically oxidized. The masking layer and the oxidized copper layer are removed by a wet etching process, to form a copper plug in the via opening and a copper wire line on the copper plug. A copper interconnect structure is also disclosed.

Abstract translation: 公开了一种用于制造铜互连结构的方法。 提供具有导电区域的基板。 在基板上形成具有通路孔的绝缘层。 通孔开口暴露导电区域。 在第一绝缘层上形成铜层，并通过依次进行沉积和回流处理而填充通孔。 掩模层形成在铜层上以覆盖通孔开口。 被掩蔽层未覆盖的铜层被各向异性地氧化。 通过湿蚀刻工艺除去掩模层和氧化铜层，以在通孔开口形成铜塞，在铜插塞上形成铜线。 还公开了铜互连结构。

公开(公告)号：US20130071992A1

公开(公告)日：2013-03-21

申请号：US13237975

申请日：2011-09-21

Applicant: Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/762

CPC classification number: H01L21/762 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02664

Abstract: A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer.

Abstract translation: 提供半导体工艺。 绝缘层形成在半导体衬底上。 去除绝缘层的一部分，以便形成多个隔离结构和布置在隔离结构之间并露出半导体衬底的网孔。 通过进行选择性生长处理，从由网眼露出的半导体衬底的表面形成半导体层，使得隔离结构设置在半导体层中。

公开(公告)号：US20120276730A1

公开(公告)日：2012-11-01

申请号：US13095008

申请日：2011-04-27

Applicant: Kuo Hui Su ,  Yi Nan Chen ,  Hsien Wen Liu

Inventor： Kuo Hui Su ,  Yi Nan Chen ,  Hsien Wen Liu

IPC: H01L21/28

CPC classification number: H01L21/28202 ,  H01L21/28185

Abstract: A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; performing an oxygen treating process to implant oxygen into the nitride layer; and performing a thermal treating process to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure.

Abstract translation: 一种用于制造栅极电介质层的方法包括以下步骤：在半导体衬底上形成电介质层; 进行氮处理工艺以在介电层上形成氮化物层; 执行氧处理工艺以将氧注入到氮化物层中; 并进行热处理工艺以形成栅介质层。 可以在栅极介质层上形成栅极层的步骤以形成栅极结构。

公开(公告)号：US20120270408A1

公开(公告)日：2012-10-25

申请号：US13093838

申请日：2011-04-25

Applicant: Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/31

CPC classification number: H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: A manufacturing method of a gate dielectric layer that includes a nitride layer and an oxide layer is provided. A substrate is provided. A nitridation treatment is performed to form the nitride layer on the substrate. An oxidation treatment is performed subsequent to the formation of the nitride layer to form the oxide layer between the nitride layer and the substrate.

Abstract translation: 提供了包括氮化物层和氧化物层的栅极电介质层的制造方法。 提供基板。 进行氮化处理以在衬底上形成氮化物层。 在形成氮化物层之后进行氧化处理，以在氮化物层和衬底之间形成氧化物层。

公开(公告)号：US20120267760A1

公开(公告)日：2012-10-25

申请号：US13093840

申请日：2011-04-25

Applicant: Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/75

Abstract: A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.

Abstract translation: 提供电容器及其制造方法。 电容器包括第一电极，第一金属层，电介质层和第二电极。 第一电极设置在基板上。 第一金属层设置在第一电极上。 电介质层设置在第一金属层上，其中第一金属层的材料不与电介质层的材料反应。 第二电极设置在电介质层上。