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    Memory device with short read time
    21.
    发明授权
    Memory device with short read time 有权
    具有短读取时间的存储器件

    公开(公告)号：US06515896B1

    公开(公告)日：2003-02-04

    申请号：US09910823

    申请日：2001-07-24

    Applicant: Lung T. Tran

    Inventor： Lung T. Tran

    IPC: G11C1114

    CPC classification number: G11C11/16 ,  G11C11/15

    Abstract: The memory device includes a memory array of memory cells, and intersecting word lines and bit lines. At one end of the array, a bank of read/write select switches selectively couples the bit lines to a column write current source, and to a reference potential voltage. A bank of sense amplifier select switches selectively couples the bit lines to a sense amplifier, which is also at the reference potential voltage. Each switch in the bank of sense amplifier select switches may be closed to allow the sense amplifier to sense the binary state of a selected memory cell. The switches in the bank of read/write select switches may each be closed to couple a selected bit line to reference potential voltage. During read operations, the bank of sense amplifier select switches and the bank of read write select switches are operated so that ends of the bit lines are coupled to the reference potential voltage, so that the memory array remains in an equipotential state. Because the memory array remains in the equipotential state, no settling time is required for the memory array due to multiplexing to the sense amplifier. Read operations are therefore faster than in conventional devices.

    Abstract translation: 存储器件包括存储器单元的存储器阵列，以及相交的字线和位线。 在阵列的一端，一组读/写选择开关选择性地将位线耦合到列写入电流源和参考电位电压。 读出放大器选择开关组选择性地将位线耦合到也在参考电位电压的读出放大器。 读出放大器选择开关组中的每个开关可以闭合，以允许读出放大器感测所选存储单元的二进制状态。 读/写选择开关组中的开关可以分别关闭以将所选位线耦合到参考电位电压。 在读取操作期间，读出放大器组选择开关，并且操作读取写入选择开关组，使得位线的端部耦合到参考电位电压，使得存储器阵列保持等电位状态。 由于存储器阵列保持在等电位状态，由于与读出放大器的多路复用，存储器阵列不需要建立时间。 因此，读操作比传统设备更快。

    Magneto-resistive device including soft reference layer having embedded conductors
    22.
    发明授权
    Magneto-resistive device including soft reference layer having embedded conductors 有权
    磁阻器件包括具有嵌入导体的软参考层

    公开(公告)号：US06504221B1

    公开(公告)日：2003-01-07

    申请号：US09963932

    申请日：2001-09-25

    Applicant: Lung T. Tran ,  Manish Sharma ,  Manoj K. Bhattacharyya

    Inventor： Lung T. Tran ,  Manish Sharma ,  Manoj K. Bhattacharyya

    IPC: G11C1115

    CPC classification number: G11C11/16 ,  B82Y10/00 ,  H01L27/222

    Abstract: A magnetic memory device includes a data ferromagnetic layer having a magnetization that can be oriented in either of two directions, a reference layer, and a spacer layer between the data and reference layers. The reference layer includes a dielectric layer, first and second conductors separated by the dielectric layer, and a ferromagnetic cladding on the first and second conductors. The memory device may be read by temporarily setting the magnetization of the reference layer to a known orientation, and determining a resistance state of the device.

    Abstract translation: 磁存储器件包括具有可以在两个方向中的任一个方向上定向的磁化的数据铁磁层，参考层和数据和参考层之间的间隔层。 参考层包括电介质层，由电介质层分开的第一和第二导体以及第一和第二导体上的铁磁包层。 可以通过将参考层的磁化临时设置为已知取向来读取存储器件，并且确定器件的电阻状态。

    MRAM device including write circuit for supplying word and bit line current having unequal magnitudes
    24.
    发明授权
    MRAM device including write circuit for supplying word and bit line current having unequal magnitudes 有权
    MRAM器件包括用于提供具有不等量幅度的字和位线电流的写电路

    公开(公告)号：US6111783A

    公开(公告)日：2000-08-29

    申请号：US334485

    申请日：1999-06-16

    Applicant: Lung T. Tran ,  James A. Brug

    Inventor： Lung T. Tran ,  James A. Brug

    IPC: G11C11/15 ,  G11C11/14

    CPC classification number: G11C11/15

    Abstract: Data is written to a memory cell of a Magnetic Random Access Memory ("MRAM") device by supplying currents having substantially unequal magnitudes to word and bit lines crossing that memory cell. The substantially higher magnitude current may be supplied to the word lines.

    Abstract translation: 通过向与该存储单元相交的字和位线提供具有基本上不相等幅度的电流将数据写入磁随机存取存储器（“MRAM”）器件的存储单元。 可以将大幅度更大的电流提供给字线。

    Memory device array having a pair of magnetic bits sharing a common conductor line
    26.
    发明授权
    Memory device array having a pair of magnetic bits sharing a common conductor line 有权
    具有共享公共导体线的一对磁性位的存储器件阵列

    公开(公告)号：US06879508B2

    公开(公告)日：2005-04-12

    申请号：US10692617

    申请日：2003-10-24

    Applicant: Lung T. Tran

    Inventor： Lung T. Tran

    IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08 ,  G11C17/00

    CPC classification number: G11C11/16 ,  H01L27/224

    Abstract: A data storage device having parallel memory planes is disclosed. Each memory plane includes a first resistive cross point plane of memory cells, a second resistive cross point plane of memory cells, a plurality of conductive word lines shared between the first and second planes of memory cells, a plurality of bit lines, each bit line coupling one or more cells from the first plane to another memory cell in the second plane, and a plurality of unidirectional elements. Further, the one unidirectional element couples a first memory cell from the first plane to a selected word line and a selected bit line in a first conductive direction and a second unidirectional element couples a second cell from the second plane to the selected word line and selected bit line in a second conductive direction. The device further provides for a unidirectional conductive path to form from a memory cell in the first plane to a memory cell in the second plane sharing the same bit line.

    Abstract translation: 公开了一种具有并行存储器平面的数据存储装置。 每个存储器平面包括存储器单元的第一电阻交叉点平面，存储器单元的第二电阻交叉点平面，在存储器单元的第一和第二平面之间共享的多个导电字线，多个位线，每个位线 将一个或多个单元从第一平面耦合到第二平面中的另一个存储单元，以及多个单向元件。 此外，一个单向元件将第一存储器单元从第一平面耦合到所选择的字线，并且第一导电方向上的选定位线和第二单向元件将第二单元从第二平面耦合到所选择的字线并选择 位线在第二导电方向上。 该装置还提供从第一平面中的存储器单元形成到共享相同位线的第二平面中的存储器单元的单向导电路径。

    Resistive cross point memory arrays having a charge injection differential sense amplifier
    28.
    发明授权
    Resistive cross point memory arrays having a charge injection differential sense amplifier 有权
    具有电荷注入差分读出放大器的电阻式交叉点存储器阵列

    公开(公告)号：US06597598B1

    公开(公告)日：2003-07-22

    申请号：US10136782

    申请日：2002-04-30

    Applicant: Lung T. Tran ,  Frederick A. Perner

    Inventor： Lung T. Tran ,  Frederick A. Perner

    IPC: G11C1700

    CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C11/16 ,  G11C16/28

    Abstract: A data storage device that includes a resistive cross point array of memory cells, a plurality of word lines, and a plurality of bit lines, and a sense amplifier that utilizes an injection charge amplifier is disclosed. The memory cells are arranged into multiple groups of one or more memory cells. The injection charge amplifier determines whether a sensed memory cell is in a first or second resistive state as compared to a reference cell.

    Abstract translation: 公开了一种数据存储装置，其包括存储器单元的电阻交叉点阵列，多个字线和多个位线，以及利用注入电荷放大器的读出放大器。 存储单元被布置成多组一个或多个存储单元。 注入电荷放大器确定感测到的存储单元是否处于与参考单元相比的第一或第二电阻状态。

    Memory device having dual tunnel junction memory cells
    30.
    发明授权
    Memory device having dual tunnel junction memory cells 失效
    具有双隧道结存储单元的存储器件

    公开(公告)号：US06541792B1

    公开(公告)日：2003-04-01

    申请号：US09951378

    申请日：2001-09-14

    Applicant: Lung T. Tran ,  Heon Lee

    Inventor： Lung T. Tran ,  Heon Lee

    IPC: H01L2904

    CPC classification number: H01L27/101 ,  G11C17/16

    Abstract: A memory device includes memory cells having two tunnel junctions in series. In order to program a selected memory cell, a first tunnel junction in the selected memory cell is blown. Blowing the first tunnel junction creates a short across the first tunnel junction, and changes the resistance of the selected memory cell from a first state to a second state. The change in resistance is detectable by a read process. The second tunnel junction has different anti-fuse characteristic than the first tunnel junction, and is not shorted by the write process. The second tunnel junction can therefore provide an isolation function to the memory cell after the first tunnel junction is blown.

    Abstract translation: 存储器件包括具有串联的两个隧道结的存储单元。 为了对所选择的存储器单元进行编程，所选择的存储器单元中的第一隧道结被熔断。 吹制第一隧道结在第一隧道结上产生短路，并且将所选择的存储器单元的电阻从第一状态改变到第二状态。 电阻的变化可以通过读取过程来检测。 第二个隧道结具有与第一个隧道结不同的抗熔断特性，并且不会因写入过程而短路。 因此，第二隧道结可以在第一隧道结被吹制之后向存储器单元提供隔离功能。

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