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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    22.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20080205144A1

    公开(公告)日：2008-08-28

    申请号：US11971334

    申请日：2008-01-09

    Applicant: Yasue YAMAMOTO ,  Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Toshiaki KAWASAKI

    Inventor： Yasue YAMAMOTO ,  Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Toshiaki KAWASAKI

    IPC: G11C16/04 ,  G11C16/06

    CPC classification number: G11C16/0441 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.

    Abstract translation: 在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器 擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。 这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。

    Semiconductor storage device including electrical fuse module
    23.
    发明授权
    Semiconductor storage device including electrical fuse module 有权
    半导体存储装置包括电熔丝模块

    公开(公告)号：US07397720B2

    公开(公告)日：2008-07-08

    申请号：US11501039

    申请日：2006-08-09

    Applicant: Shinichi Sumi ,  Hirohito Kikukawa ,  Yasuhiro Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki ,  Ryuji Nishihara ,  Yasue Yamamoto

    Inventor： Shinichi Sumi ,  Hirohito Kikukawa ,  Yasuhiro Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki ,  Ryuji Nishihara ,  Yasue Yamamoto

    IPC: G11C17/18 ,  G11C17/00

    CPC classification number: G11C17/16 ,  G11C17/165 ,  G11C29/027 ,  G11C29/785 ,  G11C2229/763

    Abstract: Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.

    Abstract translation: 提供多级的电熔丝块（100），每个级包括多个电熔丝芯（101）。 电熔丝块（100）包括由移位寄存器（107）构成的程序移位寄存器块（103），它们被设置用于相应的电熔丝芯（101），顺序发送编程使能信号FPGI，并输出编程使能信号 FPGI连接到电熔丝芯（101）的NMOS晶体管（105）。 当根据编程判定信号PBn执行编程时，程序移位寄存器块（103）发送程序使能信号FPGI。 当不执行编程时，程序移位寄存器块（103）跳过编程使能信号FPGI。

    Semiconductor memory device
    25.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20080112210A1

    公开(公告)日：2008-05-15

    申请号：US11905532

    申请日：2007-10-02

    Applicant: Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Yasue YAMAMOTO

    Inventor： Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Yasue YAMAMOTO

    IPC: G11C11/00 ,  G11C8/00

    CPC classification number: G11C11/16 ,  G11C7/12 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0028 ,  G11C2213/72

    Abstract: A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow therethrough by application of a positive voltage to the other terminal thereof using a potential at one terminal (second node) thereof as a reference. The first node is connected to the corresponding column select line and the second node is connected to the corresponding row select line. Then, to a non-selected row select line, a potential higher than when the row select line is selected is applied by using a row control circuit. By using column-select-line driver circuits, predetermined potentials corresponding to a non-selection period, a data write period, a reset period, and a data read period are applied to the column select line.

    Abstract translation: 存储单元通过串联连接可变电阻元件，该可变电阻元件具有通过使用其另一端子处的电位作为参考而将正电压施加到其一个端子（第一节点）而变化的电阻，以及允许 使用在其一个端子（第二节点）处的电位作为参考，通过向其另一端施加正电压而流过其中的电流。 第一个节点连接到相应的列选择线，第二个节点连接到相应的行选择行。 然后，对于未选择的行选择线，通过使用行控制电路来应用比选择行选择线高的电位。 通过使用列选择线驱动电路，将对应于非选择周期，数据写入周期，复位周期和数据读取周期的预定电位施加到列选择线。

    System LSI
    26.
    发明申请
    System LSI 有权
    系统LSI

    公开(公告)号：US20070097573A1

    公开(公告)日：2007-05-03

    申请号：US11526816

    申请日：2006-09-26

    Applicant: Yasuhiro Agata ,  Toshiaki Kawasaki ,  Masanori Shirahama ,  Ryuji Nishihara ,  Shinichi Sumi ,  Yasue Yamamoto ,  Hirohito Kikukawa

    Inventor： Yasuhiro Agata ,  Toshiaki Kawasaki ,  Masanori Shirahama ,  Ryuji Nishihara ,  Shinichi Sumi ,  Yasue Yamamoto ,  Hirohito Kikukawa

    IPC: H02H3/20

    CPC classification number: G11C5/063 ,  G11C5/14 ,  G11C17/165 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

    Abstract translation: 系统LSI包括输入/​​输出部分和逻辑电路部分。 输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供 来自I / O电源单元的源电源。 逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。

    Nonvolatile semiconductor memory device and method for fabricating the same
    27.
    发明授权
    Nonvolatile semiconductor memory device and method for fabricating the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US07184304B2

    公开(公告)日：2007-02-27

    申请号：US11191963

    申请日：2005-07-29

    Applicant: Ryuji Nishihara ,  Masashi Agata ,  Toshiaki Kawasaki ,  Masanori Shirahama

    Inventor： Ryuji Nishihara ,  Masashi Agata ,  Toshiaki Kawasaki ,  Masanori Shirahama

    IPC: G11C16/04

    CPC classification number: G11C16/12

    Abstract: A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.

    Abstract translation: 半导体存储器件包括：用于存储互补数据的第一和第二位单元; 用于输出所选数据信号的扫描电路; 接收所述扫描电路的输出并选择所述位单元之一的位单元选择器; 以及用于控制数据写入的数据写入控制电路。 用于存储“0”的所有位单元的写入路径不被选择，并且数据仅被写入用于存储“1”的位单元中，从而实现了步骤执行的写入操作。

    Semiconductor device including a plurality of circuit blocks provided on a chip and having different functions
    28.
    发明授权
    Semiconductor device including a plurality of circuit blocks provided on a chip and having different functions 有权
    半导体器件包括设置在芯片上并具有不同功能的多个电路块

    公开(公告)号：US07183829B2

    公开(公告)日：2007-02-27

    申请号：US10773315

    申请日：2004-02-09

    Applicant: Naoki Kuroda ,  Masanori Shirahama

    Inventor： Naoki Kuroda ,  Masanori Shirahama

    IPC: H03H11/26

    CPC classification number: H03H11/265

    Abstract: A logic circuit block and a memory circuit block are provided on a semiconductor chip. A timing adjustment circuit block for adjusting the propagation timing of signals is provided on a line between the circuit blocks. A timing adjustment circuit unit includes: a delay element block including a plurality of delay elements for adding different delay amounts to the inter-block signals; a counter circuit block for receiving a timing adjustment control signal from the timing adjustment circuit block; and a fuse circuit block in which a fuse is melted down based on a fuse information signal held by the counter circuit block after a timing verification and which replaces the function of the counter circuit block.

    Abstract translation: 逻辑电路块和存储电路块设置在半导体芯片上。 在电路块之间的一条线上提供用于调整信号的传播定时的定时调整电路块。 定时调整电路单元包括：延迟元件块，包括用于向块间信号添加不同延迟量的多个延迟元件; 用于从定时调整电路块接收定时调整控制信号的计数器电路块; 以及熔断器电路块，其中熔丝在定时验证之后基于由计数器电路块保持的熔丝信息信号而熔化，并且替代了计数器电路块的功能。

    Low latency dynamic random access memory
    29.
    发明授权
    Low latency dynamic random access memory 有权
    低延迟动态随机存取存储器

    公开(公告)号：US06226223B1

    公开(公告)日：2001-05-01

    申请号：US09511901

    申请日：2000-02-23

    Applicant: Masanori Shirahama ,  Tsutomu Fujita ,  Masashi Agata ,  Kazunari Takahashi ,  Naoki Kuroda

    Inventor： Masanori Shirahama ,  Tsutomu Fujita ,  Masashi Agata ,  Kazunari Takahashi ,  Naoki Kuroda

    IPC: G11C800

    CPC classification number: G11C7/222 ,  G11C7/22 ,  G11C11/24 ,  G11C11/4076

    Abstract: In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.

    Abstract translation: 在具有多个存储器单元的半导体存储器件中，每个存储单元包括一个电荷存储器件和两个用于传送其电荷的转移器件，这些存储器单元是可以被访问的，没有从外部提供的选择信号。 存储器件包括用于产生第一和第二互补时钟信号的时钟发生器。 响应于第一和第二时钟信号，交替地激活第一字线和第二字线之一中的一个。 具体地，第一时钟信号通过激活第一字线和第一晶体管使得可通过第一位线访问存储单元，而第二时钟信号通过激活第二字线和第二晶体管使存储单元通过第二位线访问 。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    30.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20100238735A1

    公开(公告)日：2010-09-23

    申请号：US12792295

    申请日：2010-06-02

    Applicant: Yasue YAMAMOTO ,  Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Toshiaki KAWASAKI

    Inventor： Yasue YAMAMOTO ,  Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Toshiaki KAWASAKI

    IPC: G11C16/04 ,  H01L29/94

    CPC classification number: G11C16/0441 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.

    Abstract translation: 在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器 擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。 这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。

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