公开(公告)号：US08329516B2

公开(公告)日：2012-12-11

申请号：US13404051

申请日：2012-02-24

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L21/44 ,  H01L21/336

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0673 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S977/813 ,  Y10S977/842 ,  Y10S977/843 ,  Y10S977/89 ,  Y10S977/891

Abstract: A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

Abstract translation: 多个纳米线在与第一基板垂直的第一方向上在第一基板上生长。 覆盖纳米线的绝缘层形成在第一基板上，以限定包括纳米线和绝缘层的纳米线块。 移动纳米线块，使得每个纳米线沿平行于第一基底的第二方向排列。 绝缘层被部分去除以部分地暴露纳米线。 形成覆盖暴露的纳米线的栅极线。 将杂质注入到与栅极线相邻的纳米线的部分中。

公开(公告)号：US07994581B2

公开(公告)日：2011-08-09

申请号：US12506656

申请日：2009-07-21

Applicant: Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

Inventor： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

IPC: H01L27/092

CPC classification number: H01L27/124 ,  B82Y10/00 ,  H01L27/095 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/45 ,  H01L29/7839 ,  H01L29/78681 ,  H01L29/7869

Abstract: In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second transistor having a second conductivity type are positioned on the substrate, respectively. The first transistor includes a first gate positioned on a first surface of the channel material through a medium of a gate insulation layer and a pair of ohmic contacts positioned on a second surface of the channel material and crossing over both side portions of the first gate electrode, respectively. The second transistor includes a second gate positioned on the first surface of the channel material through a medium of the gate insulation layer and a pair of Schottky contacts positioned on the second surface of the channel material and crossing over both side portions of the second gate electrode, respectively.

Abstract translation: 在互补金属氧化物半导体（CMOS）晶体管及其制造方法中，在基板上设置具有第一导电类型的半导体沟道材料。 具有第一导电类型的第一晶体管和具有第二导电类型的第二晶体管分别位于衬底上。 第一晶体管包括位于通道材料的第一表面上的第一栅极，该第一栅极通过栅极绝缘层的介质和位于沟道材料的第二表面上的一对欧姆触点，并且跨越第一栅电极的两侧部分 ， 分别。 第二晶体管包括通过栅极绝缘层的介质定位在沟道材料的第一表面上的第二栅极和位于沟道材料的第二表面上并与第二栅电极的两侧部分交叉的一对肖特基触点 ， 分别。

公开(公告)号：US20110147714A1

公开(公告)日：2011-06-23

申请号：US12814824

申请日：2010-06-14

Applicant: Seung Hun HONG ,  Byeong Ju KIM ,  Moon Sook LEE

Inventor： Seung Hun HONG ,  Byeong Ju KIM ,  Moon Sook LEE

IPC: H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  G01N27/4145 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696

Abstract: A field-effect transistor has at least one electrode disposed independently of source and drain electrodes and in direct contact with the surface of a semiconductor channel to form a schottky barrier, so that it is possible to easily control the schottky barrier.

Abstract translation: 场效应晶体管具有独立于源电极和漏电极设置的至少一个电极，并且与半导体沟道的表面直接接触以形成肖特基势垒，使得可以容易地控制肖特基势垒。

公开(公告)号：US07480174B2

公开(公告)日：2009-01-20

申请号：US11762483

申请日：2007-06-13

Applicant: Moon-Sook Lee ,  In-Gyu Baek

Inventor： Moon-Sook Lee ,  In-Gyu Baek

IPC: G11C11/00

CPC classification number: G11C13/00 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to establish a resistance of the transition metal oxide layer and applying a second electric pulse to the transition metal oxide layer for a second period, longer than the first period, to increase the resistance of the transition metal oxide layer. Related devices are also disclosed.

Abstract translation: 一种对包括过渡金属氧化物层的非易失性存储器件进行编程的方法包括：将第一电脉冲施加到过渡金属氧化物层第一周期以建立过渡金属氧化物层的电阻并向第二电脉冲施加第二电脉冲 过渡金属氧化物层，延长第一周期，以增加过渡金属氧化物层的电阻。 还公开了相关设备。

公开(公告)号：US20090008620A1

公开(公告)日：2009-01-08

申请号：US12200190

申请日：2008-08-28

Applicant: In-Gyu Baek ,  Moon-Sook Lee

Inventor： In-Gyu Baek ,  Moon-Sook Lee

IPC: H01L47/00

CPC classification number: H01L27/115 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula MxOy. In the chemical formula, the characters “M”, “O”, “x” and “y” indicate transition metal, oxygen, a transitional metal composition and an oxygen composition, respectively. The transition metal oxide layer pattern has excessive transition metal content in comparison to a stabilized transition metal oxide layer pattern. Methods of fabricating the non-volatile memory cells are also provided.

Abstract translation: 提供了使用过渡金属氧化物层作为数据存储材料层的非易失性存储单元。 非易失性存储单元包括彼此重叠的下电极和上电极。 在下电极和上电极之间设置过渡金属氧化物层图案。 过渡金属氧化物层图案由化学式MxOy表示。 在化学式中，字母“M”，“O”，“x”和“y”分别表示过渡金属，氧，过渡金属组成和氧组成。 与稳定的过渡金属氧化物层图案相比，过渡金属氧化物层图案具有过量的过渡金属含量。 还提供了制造非易失性存储单元的方法。

公开(公告)号：US07420198B2

公开(公告)日：2008-09-02

申请号：US11179319

申请日：2005-07-12

Applicant: In-Gyu Baek ,  Moon-Sook Lee

Inventor： In-Gyu Baek ,  Moon-Sook Lee

IPC: H01L47/00

CPC classification number: H01L27/115 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula MxOy. In the chemical formula, the characters “M”, “O”, “x” and “y” indicate transition metal, oxygen, a transitional metal composition and an oxygen composition, respectively. The transition metal oxide layer pattern has excessive transition metal content in comparison to a stabilized transition metal oxide layer pattern. Methods of fabricating the non-volatile memory cells are also provided.

Abstract translation: 提供了使用过渡金属氧化物层作为数据存储材料层的非易失性存储单元。 非易失性存储单元包括彼此重叠的下电极和上电极。 在下电极和上电极之间设置过渡金属氧化物层图案。 过渡金属氧化物层图案由化学式M X x O Y y表示。 在化学式中，字母“M”，“O”，“x”和“y”分别表示过渡金属，氧，过渡金属组成和氧组成。 与稳定的过渡金属氧化物层图案相比，过渡金属氧化物层图案具有过量的过渡金属含量。 还提供了制造非易失性存储单元的方法。

公开(公告)号：US20080191255A1

公开(公告)日：2008-08-14

申请号：US12108255

申请日：2008-04-23

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L43/08 ,  H01L21/00

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned with the node contact holes, respectively, and are disposed so as to protrude upward from the diffusion preventive layer. Lower electrodes are disposed on the diffusion preventive layer that cover the node conductive layer patterns, respectively. Thicknesses of the lower electrodes are gradually reduced from a line extending from upper surfaces of the node conductive layer patterns toward the diffusion preventive layer.

Abstract translation: 铁电随机存取存储器（FRAM）在衬底上包括半导体衬底和层间绝缘层。 扩散防止层在层间绝缘层上。 扩散防止层和层间绝缘层在其中形成有两个节点接触孔。 节点导电层图案分别与节点接触孔对准，并且设置成从扩散防止层向上突出。 下电极分别设置在覆盖节点导电层图案的扩散防止层上。 下部电极的厚度从从节点导电层图案的上表面朝向扩散防止层延伸的线逐渐减小。

公开(公告)号：US20070045692A1

公开(公告)日：2007-03-01

申请号：US11511469

申请日：2006-08-29

Applicant: Dong-Chul Kim ,  In-Gyu Baek ,  Young-Kwan Cha ,  Moon-Sook Lee ,  Sang-Jin Park

Inventor： Dong-Chul Kim ,  In-Gyu Baek ,  Young-Kwan Cha ,  Moon-Sook Lee ,  Sang-Jin Park

IPC: H01L29/94

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

Abstract: Nonvolatile memory devices and methods of manufacturing the same are provided. The nonvolatile memory devices may include an oxide layer formed of a resistance conversion material, a lower electrode, a nano-wire layer formed of a transition metal on the lower electrode, and an upper electrode formed on the oxide layer. According to example embodiments, a reset current may be stabilized by unifying a current path on the oxide layer.

Abstract translation: 提供了非易失性存储器件及其制造方法。 非易失性存储器件可以包括由电阻转换材料，下电极，由下电极上的过渡金属形成的纳米线层和形成在氧化物层上的上电极形成的氧化物层。 根据示例性实施例，可以通过统一氧化物层上的电流路径来稳定复位电流。

公开(公告)号：US20060183252A1

公开(公告)日：2006-08-17

申请号：US11402377

申请日：2006-04-12

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L21/00

CPC classification number: H01L28/60 ,  H01L27/10855 ,  H01L27/11502 ,  H01L27/11507

Abstract: Forming a ferroelectric memory device can include forming an insulating layer on a substrate, forming a sacrificial layer on the first insulating layer so that the insulating layer is between the sacrificial layer and the substrate, and forming a contact hole extending through the sacrificial layer and the insulating layer. A conductive contact plug can be formed in the contact hole. After forming the conductive contact plug in the contact hole, the sacrificial layer can be removed so that the conductive contact plug extends beyond the insulating layer, and so that sidewalls of the conductive contact plug extending beyond the insulating layer are exposed. A first electrode can be formed on exposed portions of the conductive contact plug, a ferroelectric layer can be formed on the first electrode, and a second electrode can be formed on the ferroelectric layer such that the ferroelectric layer is between the first and second electrodes. Related structures are also discussed.

Abstract translation: 形成铁电存储器件可以包括在衬底上形成绝缘层，在第一绝缘层上形成牺牲层，使得绝缘层位于牺牲层和衬底之间，并形成延伸穿过牺牲层的接触孔和 绝缘层。 可以在接触孔中形成导电接触插塞。 在接触孔中形成导电接触插塞之后，可以去除牺牲层，使得导电接触插塞延伸超过绝缘层，并且使得延伸超过绝缘层的导电接触插塞的侧壁被暴露。 第一电极可以形成在导电接触插塞的暴露部分上，可以在第一电极上形成铁电层，并且可以在铁电层上形成第二电极，使得铁电层位于第一和第二电极之间。 还讨论了相关结构。

公开(公告)号：US07067329B2

公开(公告)日：2006-06-27

申请号：US10273115

申请日：2002-10-17

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L21/00

CPC classification number: H01L28/60 ,  H01L27/10855 ,  H01L27/11502 ,  H01L27/11507

Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The device includes a substrate where a conductive region is formed and an interlayer insulating layer. The interlayer insulating layer is stacked on the substrate and has a contact hole exposing the conductive region. The contact hole is filled with a contact plug having a projection over the interlayer insulating layer. The projection of the contact plug is covered with a capacitor including a lower electrode, a ferroelectric layer pattern, and an upper electrode. A width of the projection is preferably greater than that of the contact hole and smaller than that of the lower electrode. The method includes forming lower and upper interlayer insulating layers on a substrate where a conductive region is formed. The lower and upper interlayer insulating layers have a contact hole exposing the conductive region. After forming a conductive contact plug filling the contact hole, the upper interlayer insulating layer is removed to expose the lower interlayer insulating layer. Thus, an upper portion of the contact plug that is higher than the lower interlayer insulating layer is projected. Continuously, a lower electrode, a ferroelectric layer pattern, and an upper electrode sequentially cover the projected contact plug to form a capacitor. The upper interlayer insulating layer is preferably made of a material having an etch selectivity with respect to the lower interlayer insulating layer. The contact hole is preferably formed such that a width of the contact hole formed in the upper interlayer insulating layer is greater than that of the contact hole formed in the lower interlayer insulating layer.

Abstract translation: 提供了一种铁电存储器件及其制造方法。 该器件包括其中形成导电区域的基板和层间绝缘层。 层间绝缘层层叠在基板上，并具有使导电区域露出的接触孔。 接触孔填充有在层间绝缘层上方具有突起的接触插塞。 接触插头的突起被包括下电极，铁电层图案和上电极的电容器覆盖。 突起的宽度优选大于接触孔的宽度，并且小于下部电极的宽度。 该方法包括在形成有导电区域的基板上形成下层和上层间绝缘层。 下层和上层间绝缘层具有暴露导电区域的接触孔。 在形成填充接触孔的导电接触塞之后，去除上部层间绝缘层以露出下部层间绝缘层。 因此，高于下层间绝缘层的接触插塞的上部被突出。 连续地，下电极，铁电层图案和上电极顺序地覆盖投影的接触插塞以形成电容器。 上层间绝缘层优选由相对于下层间绝缘层具有蚀刻选择性的材料制成。 接触孔优选形成为使得形成在上层间绝缘层中的接触孔的宽度大于形成在下层间绝缘层中的接触孔的宽度。