公开(公告)号：US20110215288A1

公开(公告)日：2011-09-08

申请号：US13108174

申请日：2011-05-16

申请人： Yuichi MATSUI ,  Tomio IWASAKI ,  Norikatsu TAKAURA ,  Kenzo KUROTSUCHI

发明人： Yuichi MATSUI ,  Tomio IWASAKI ,  Norikatsu TAKAURA ,  Kenzo KUROTSUCHI

IPC分类号： H01L45/00

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675

摘要： Since a chalcogenide material has low adhesion to a silicon oxide film, there is a problem in that it tends to separate from the film during the manufacturing step of a phase change memory. In addition, since the chalcogenide material has to be heated to its melting point or higher during resetting (amorphization) of the phase change memory, there is a problem of requiring extremely large rewriting current. An interfacial layer includes an extremely thin insulator or semiconductor having the function as both an adhesive layer and a high resistance layer (thermal resistance layer) is inserted between chalcogenide material layer/interlayer insulative film and between chalcogenide material layer/plug.

摘要翻译： 由于硫族化物材料对氧化硅膜的粘附性低，所以存在在相变存储器的制造工序中与膜分离的问题。 此外，由于在相变存储器的复位（非晶化）期间必须将硫属化物材料加热至其熔点以上，所以存在需要非常大的重写电流的问题。 界面层包括极薄的绝缘体或半导体，具有将粘合剂层和高电阻层（热电阻层）两者插入到硫族化物材料层/层间绝缘膜之间以及硫族化物材料层/插塞之间的功能。

公开(公告)号：US07859896B2

公开(公告)日：2010-12-28

申请号：US12162702

申请日：2006-02-02

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Yoshihisa Fujisaki

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Yoshihisa Fujisaki

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/24

摘要： A semiconductor device for high-speed reading and which has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, information is programmed by a first pulse (reset operation) for programming information flowing in the bit line, a second pulse (set operation) different from the first pulse, and information is read by a third pulse (read operation), such that the current directions of the second pulse and the third pulse are opposite to each other.

摘要翻译： 提供了一种用于高速读取并具有高数据保持特性的半导体器件。 在包括具有设置在多个字线和多个位线的交叉点的多个存储单元的存储器阵列的半导体器件中，其中每个存储器单元包括信息存储器部分和选择元件，信息由 用于对在位线中流动的信息进行编程的第一脉冲（复位操作），与第一脉冲不同的第二脉冲（设置操作），并且通过第三脉冲（读取操作）读取信息，使得第二脉冲 并且第三脉冲彼此相反。

公开(公告)号：US07767997B2

公开(公告)日：2010-08-03

申请号：US12169818

申请日：2008-07-09

申请人： Yoshitaka Sasago ,  Motoyasu Terao ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Tomoyuki Kodama ,  Nobuyuki Arasawa

发明人： Yoshitaka Sasago ,  Motoyasu Terao ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Tomoyuki Kodama ,  Nobuyuki Arasawa

IPC分类号： H01L29/06 ,  H01L29/08

CPC分类号： H01L45/1206 ,  G06N3/063 ,  G11C13/0011 ,  H01L45/085 ,  H01L45/142 ,  H01L45/146 ,  H01L45/1675

摘要： A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.

摘要翻译： 具有小表面积的非易失性，复杂的半导体器件和能够切换三个或更多个电极之间的连接的简单结构。 在半导体器件中，电极中的至少一个在固体电解质中含有诸如铜或银之类的原子，能够容易地在固体电解质内移动，并且这些电极彼此面对并且施加电压通过产生或消除电压来开启和关闭电压 电极之间的导电路径。 此外，向单独的第三电极施加电压可以消除在两个电极之间形成的导电路径，而不向由导电路径连接的两个电极施加电压。

公开(公告)号：US20100171087A1

公开(公告)日：2010-07-08

申请号：US12600333

申请日：2007-05-21

申请人： Kenzo Kurotsuchi ,  Motoyasu Terao ,  Takahiro Morikawa ,  Norikatsu Takaura

发明人： Kenzo Kurotsuchi ,  Motoyasu Terao ,  Takahiro Morikawa ,  Norikatsu Takaura

IPC分类号： H01L45/00 ,  H01L21/06

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： In a semiconductor device including a phase change memory element whose memory layer is formed of a phase change material of M (additive element)-Ge (germanium)-Sb (antimony)-Te (tellurium), both of high heat resistance and stable data retention property are achieved. The memory layer has a fine structure with a different composition ratio therein, and an average composition of MαGeXSbYTeZ forming the memory layer satisfies the relations of 0≦α≦0.4, 0.04≦X≦0.4, 0≦Y≦0.3, 0.3≦Z≦0.6, and 0.03≦(α+Y).

摘要翻译： 在包括由M（添加元素）-Ge（锗）-Sb（锑）-Te（碲）的相变材料形成的存储层的相变存储元件的半导体器件中，高耐热性和稳定数据 保留性能得以实现。 存储层具有不同组成比的精细结构，形成记忆层的MαGeXSbYTeZ的平均组成满足0＆lt; nlE;α＆nlE; 0.4,0.04＆nlE; X＆lt; lE; 0.4,0＆amp; nlE; Y＆nlE; 0.3,0.3＆ Z＆NlE; 0.6和0.03＆nlE;（α+ Y）。

公开(公告)号：US20100058127A1

公开(公告)日：2010-03-04

申请号：US12469778

申请日：2009-05-21

申请人： Motoyasu TERAO ,  Satoru HANZAWA ,  Hitoshi KUME ,  Minoru OGUSHI ,  Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Norikatsu TAKAURA

发明人： Motoyasu TERAO ,  Satoru HANZAWA ,  Hitoshi KUME ,  Minoru OGUSHI ,  Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Norikatsu TAKAURA

IPC分类号： G06F11/26

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

公开(公告)号：US20100012917A1

公开(公告)日：2010-01-21

申请号：US12302740

申请日：2006-05-31

申请人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

发明人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

IPC分类号： H01L47/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

公开(公告)号：US20090267047A1

公开(公告)日：2009-10-29

申请号：US12430539

申请日：2009-04-27

申请人： Yoshitaka SASAGO ,  Riichiro TAKEMURA ,  Masaharu KINOSHITA ,  Toshiyuki MINE ,  Akio SHIMA ,  Hideyuki MATSUOKA ,  Mutsuko HATANO ,  Norikatsu TAKAURA

发明人： Yoshitaka SASAGO ,  Riichiro TAKEMURA ,  Masaharu KINOSHITA ,  Toshiyuki MINE ,  Akio SHIMA ,  Hideyuki MATSUOKA ,  Mutsuko HATANO ,  Norikatsu TAKAURA

IPC分类号： H01L47/00

CPC分类号： H01L27/2481 ,  H01L21/02532 ,  H01L21/02675 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

摘要： The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory and the semiconductor device. After a polysilicon forming a selection device is deposited in an amorphous state at a low temperature, the crystallization of the polysilicon and the activation of impurities are briefly performed with heat treatment by laser annealing. When laser annealing is performed, the recording material located below the silicon subjected to the crystallization is completely covered with a metal film or with the metal film and an insulating film, thereby making it possible to suppress a temperature increase at the time of performing the annealing and to reduce the thermal load of the recording material.

摘要翻译： 本发明可以通过实现半导体器件和存储器件的高性能来促进半导体存储器件的大容量，高性能和高可靠性，当半导体存储器件通过堆叠诸如ReRAM的存储器件或 相变存储器和半导体器件。 在低温下以非晶态沉积形成选择器件的多晶硅后，通过激光退火的热处理来简单地进行多晶硅的结晶化和杂质的活化。 当进行激光退火时，位于被结晶的硅下方的记录材料完全被金属膜或金属膜和绝缘膜覆盖，从而可以抑制进行退火时的温度升高 并降低记录材料的热负荷。

公开(公告)号：US20090242868A1

公开(公告)日：2009-10-01

申请号：US12370417

申请日：2009-02-12

申请人： Kenzo KUROTSUCHI ,  Motoyasu TERAO ,  Norikatsu TAKAURA ,  Yoshihisa FUJISAKI ,  Kazuo ONO ,  Yoshitaka SASAGO

发明人： Kenzo KUROTSUCHI ,  Motoyasu TERAO ,  Norikatsu TAKAURA ,  Yoshihisa FUJISAKI ,  Kazuo ONO ,  Yoshitaka SASAGO

IPC分类号： H01L45/00 ,  H01L21/28

CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641

摘要： A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change of resistance of the solid electrolyte layer, the solid electrolyte layer includes a composition, for example, of Cu—Ta—S and an ion supply layer in adjacent or close therewith as Cu—Ta—O, in which ions supplied from the ion supply layer form a conduction path in the solid electrolyte layer thereby making it possible to store information by the level of the resistance and applying the electric pulse to change the resistance, in which the ion supply layer includes crystals having, for example, a compositional ratio of: Cu—Ta—O=1:2:6 and rewriting operation can be performed stably.

摘要翻译： 固体电解质存储器存在难以稳定重写的问题，因为固体电解质中的离子量和电极的形状通过重复改写而改变。 在存储信息或通过固体电解质层的电阻变化来改变电路连接的半导体器件中，固体电解质层包括例如Cu-Ta-S的组合物和相邻的Cu-Ta-S的离子供给层 或与其接近的Cu-Ta-O，其中从离子供给层供给的离子在固体电解质层中形成传导路径，从而可以通过电阻水平存储信息并施加电脉冲以改变电阻 ，其中离子供给层包括例如以Cu-Ta-O = 1:2:6的组成比的晶体，并且可以稳定地进行重写操作。

公开(公告)号：US20090122602A1

公开(公告)日：2009-05-14

申请号：US12352668

申请日：2009-01-13

申请人： RIICHIRO TAKEMURA ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

发明人： RIICHIRO TAKEMURA ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

IPC分类号： G11C11/00 ,  G11C8/08 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

摘要翻译： 实现了高集成度和高​​速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

公开(公告)号：US20090039336A1

公开(公告)日：2009-02-12

申请号：US12176606

申请日：2008-07-21

申请人： Motoyasu Terao ,  Yoshitaka Sasago ,  Kenzo Kurotsuchi ,  Kazuo Ono ,  Yoshihisa Fujisaki ,  Norikatsu Takaura ,  Riichiro Takemura

发明人： Motoyasu Terao ,  Yoshitaka Sasago ,  Kenzo Kurotsuchi ,  Kazuo Ono ,  Yoshihisa Fujisaki ,  Norikatsu Takaura ,  Riichiro Takemura

IPC分类号： H01L45/00

CPC分类号： G11C11/5614 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/11 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/142 ,  H01L45/1675

摘要： The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one element of a first element group of Cu, Ag, Au, Al, Zn, and Cd, contains 3-40 atom % of at least one element of a second element group of V, Nb, Ta, Cr, Mo, W, Ti, Zr, Hf, Fe, Co, Ni, Pt, Pd, Rh, Ir, Ru, Os, and lanthanoid elements, and contains 20-60 atom % of at least one element of a third element group of S, Se, and Te. The second layer contains 5-50 atom % of at least one element of the first element group, 10-50 atom % of at least one element of the second element group, and 30-70 atom % of oxygen.

摘要翻译： 提高了能够存储信息的半导体装置的性能。 存储元件的存储层由底部电极侧的第一层和顶部电极侧的第二层形成。 第一层含有20-70原子％的Cu，Ag，Au，Al，Zn和Cd的第一元素基团的至少一种元素，含有3-40原子％的至少一种元素的第二元素基团 V，Nb，Ta，Cr，Mo，W，Ti，Zr，Hf，Fe，Co，Ni，Pt，Pd，Rh，Ir，Ru，Os和镧系元素，至少含有20-60原子％ S，Se和Te的第三要素组的一个元素。 第二层含有5-50原子％的第一元素基团的至少一个元素，10-50原子％的第二元素基团的至少一个元素和30-70原子％的氧。