公开(公告)号：US5155572A

公开(公告)日：1992-10-13

申请号：US680490

申请日：1991-04-04

Applicant: Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

Inventor： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

IPC: H01L27/06 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/74

CPC classification number: H01L29/74 ,  H01L29/0821

Abstract: A vertical isolated-collector PNP transistor structure (58) comprises a P+ region (45), a N region (44) and a P- well region (46) which form the emitter, the base and the collector, respectively. The P- well region is enclosed in a N type pocket comprised of a N+ buried layer (48) and a N reach-through region (47) in contact therewith. The contact regions (46-1, 47-1) to the P- well region (46) and to the N reach-through region (47) are shorted to define a common collector contact (59). In addition, the thickness W of the P- well region (46) is so minimized to allow transistor action of the parasitic NPN transistor formed by N PNP base region (44), P- well region (46) and the N+ buried layer, (48) respectively as the collector, the base and the emitter of said PNP transistor. The PNP transistor structure (67) may be combined with a conventional NPN transistor structure (61).

Abstract translation: 垂直隔离集电极PNP晶体管结构（58）包括分别形成发射极，基极和集电极的P +区（45），N区（44）和P-阱区（46）。 P阱区被包围在与N +掩埋层（48）和N接触区域（47）组成的N型槽中。 到P阱区域（46）和N到达区域（47）的接触区域（46-1,47-1）被短路以限定公共集电极接触件（59）。 此外，P阱区域（46）的厚度W被最小化以允许由N PNP基区（44），P-阱区（46）和N +掩埋层形成的寄生NPN晶体管的晶体管作用， （48）分别作为所述PNP晶体管的集电极，基极和发射极。 PNP晶体管结构（67）可以与传统的NPN晶体管结构（61）组合。

公开(公告)号：US5089725A

公开(公告)日：1992-02-18

申请号：US604842

申请日：1990-10-26

Applicant: Pierre Mollier ,  Jean-Paul Nuez ,  Pascal Tannhof

Inventor： Pierre Mollier ,  Jean-Paul Nuez ,  Pascal Tannhof

IPC: H03K19/013 ,  H03K19/086

CPC classification number: H03K19/086 ,  H03K19/013

Abstract: The base circuit comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages and a push-pull output buffer stage connected between second and third supply voltages. The push-pull output buffer stage comprises a pull-up transistor and a pull-down transistor connected in series with the circuit output node coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by the preamplifier. Both branches of the preamplifier are tied at a first output node (M). The first branch comprises a logic block performing the desired logic function of the base circuit that is connected through a load rsistor to the second supply voltage. The logic block consists of three parallel-connected input NPN transistors, whose emitters are coupled together at the first output node for NOR operation. The second branch is comprised of a biasing/coupling block connected to the second supply voltage and coupled to the first output node and to the base (B) node of the pull-down transistor. This block ensures both the appropriate polarization of the nodes in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal from node M to node B in AC, when input transistors of the logic block are ON. and base nodes. An anti-saturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

Abstract translation: 基本电路包括连接在第一和第二电源电压之间的差分类型的自参考前置放大器（31）和连接在第二和第三电源电压之间的推挽输出缓冲级。 推挽输出缓冲级包括与耦合在其间的电路输出节点串联连接的上拉晶体管和下拉晶体管。 这些晶体管由前置放大器提供的互补和基本同时的信号S和＆amp; upbar＆S驱动。 前置放大器的两个分支都连接在第一个输出节点（M）上。 第一分支包括执行通过负载晶体管连接到第二电源电压的基本电路的期望逻辑功能的逻辑块。 逻辑块由三个并联的输入NPN晶体管组成，其发射极在第一个输出节点耦合在一起用于NOR运算。 第二分支包括连接到第二电源电压并耦合到第一输出节点和下拉晶体管的基极（B）节点的偏置/耦合模块。 该块在逻辑块的输入晶体管中确保DC中节点的适当极化，而不需要外部参考电压发生器和低阻抗路径，用于在AC中将节点M到节点B的输出信号快速信号传输 上。 和基本节点。 通常由肖特基势垒二极管（SBD）组成的抗饱和块（AB）可用于防止下拉晶体管（TDN）的饱和，从而进一步加速电路。

公开(公告)号：US5010257A

公开(公告)日：1991-04-23

申请号：US493014

申请日：1990-03-13

Applicant: Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

Inventor： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

IPC: H03K17/567 ,  H03K5/007 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

CPC classification number: H03K19/0136 ,  H03K19/09448 ,  H03K5/007

Abstract: According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a conventional way with the feedback loop connected to said output node (14). The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in a push pull configuration is reinforced to full swing (GND to VH) by the latch at the end of each transition. The state of the output node if forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15). It is a characteristic of this embodiment that the structure of CMOS interface (C2) is always independent of the logic function implemented in the conventional BICMOS logic circuit (11). More generally, the CMOS interface circuit may have various physical implementations, however, it is always comprised of CMOS FETs and it becomes active at least in one of the GND to VBE or (VH-BE) to VH range.

公开(公告)号：US08609530B2

公开(公告)日：2013-12-17

申请号：US13052262

申请日：2011-03-21

Applicant: Simon Jeannot ,  Pascal Tannhof

Inventor： Simon Jeannot ,  Pascal Tannhof

IPC: H01L21/4763

CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

Abstract translation: 一种用于在包括一系列金属水平和通孔级别的互连堆叠的金属层中形成电容结构的方法，包括以下步骤：在金属层面形成至少一个其中限定沟槽的导电轨道; 在结构上保形地形成绝缘层; 在沟槽中形成导电材料; 并平坦化结构。

公开(公告)号：US20050154802A1

公开(公告)日：2005-07-14

申请号：US10757187

申请日：2004-01-14

Applicant: Kerry Kravec ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

Inventor： Kerry Kravec ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

IPC: G06F3/00 ,  G06K9/00 ,  G06K9/64

CPC classification number: G06K9/6202 ,  G06K9/00986

Abstract: A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

Abstract translation: 并行模式检测引擎（PPDE）包括定制的多个处理单元（PU），以执行各种模式识别模式。 PU装载有不同的图案，并且要匹配的输入数据并行提供给PU。 每个模式都有一个操作码，定义当输入数据流中的特定数据与时钟周期中正在比较的对应数据匹配或不匹配时要执行的操作。 每个PU通信所选择的信息，使得PU可以被级联以使得能够匹配更长的模式或允许针对特定的输入数据流并行地处理更多的模式。

公开(公告)号：US20050138324A1

公开(公告)日：2005-06-23

申请号：US10905100

申请日：2004-12-15

Applicant: Pascal Tannhof ,  Jan Slyfield

Inventor： Pascal Tannhof ,  Jan Slyfield

IPC: G06F15/00 ,  G06F15/173

CPC classification number: G06F15/17368

Abstract: A processing unit having a dual channel bus architecture associated with a specific instruction set, configured to receive an input message and transmit an output message that is identical or derived therefrom. A message consists of one opcode, with or without associated data, used to control each processing unit depending on logic conditions stored in dedicated registers in each unit. Processing units are serially connected but can work simultaneously for a total pipelined operation. This dual architecture is organized around two channels labeled Channel 1 and Channel 2. Channel 1 mainly transmits an input message to all units while Channel 2 mainly transmits the results after processing in a unit as an output message. Depending on the logic conditions, an input message not processed in a processing unit may be transmitted to the next one without any change.

Abstract translation: 一种具有与特定指令集相关联的双通道总线架构的处理单元，其被配置为接收输入消息并发送相同或从其导出的输出消息。 消息由一个操作码组成，具有或不具有关联数据，用于根据存储在每个单元中的专用寄存器中的逻辑条件来控制每个处理单元。 处理单元串联连接，但可以同时工作进行总体流水线操作。 该双重架构围绕标记为通道1和通道2的两个通道组合。通道1主要向所有单元发送输入消息，而通道2主要在以单元处理之后将结果作为输出消息发送。 根据逻辑条件，在处理单元中未处理的输入消息可以被发送到下一个，而没有任何改变。

公开(公告)号：US06782373B2

公开(公告)日：2004-08-24

申请号：US09682035

申请日：2001-07-12

Applicant: Ghislain Imbert de Tremiolles ,  Pascal Tannhof

Inventor： Ghislain Imbert de Tremiolles ,  Pascal Tannhof

IPC: G06N302

CPC classification number: G06K9/6215 ,  G06K9/6276 ,  G06N3/063

Abstract: The method and circuits of the present invention aim to associate a norm to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. The set of norms, referred to as the “component” norms is memorized in specific memorization means in the ANN. In a first embodiment, the ANN is provided with a global memory, common for all the neurons of the ANN, that memorizes all the component norms. For each component of the input pattern, all the neurons perform the elementary (or partial) distance calculation with the corresponding prototype components stored therein during the distance evaluation process using the associated component norm. The distance elementary calculations are then combined using a “distance” norm to determine the final distance between the input pattern and the prototypes stored in the neurons. In another embodiment, the set of component norms is memorized in the neurons themselves in the prototype memorization means, so that the global memory is no longer physically necessary. This implementation allows to significantly optimize the consumed silicon area when the ANN is integrated in a silicon chip.

Abstract translation: 本发明的方法和电路旨在将距离评估过程中给出的输入模式的每个分量与基于输入空间映射算法的人造神经网络（ANN）相关联。 被称为“组件”规范的一套规范被记录在ANN中的具体记忆手段中。 在第一实施例中，ANN被提供有存储ANN的所有神经元的全局存储器，其存储所有的分量规范。 对于输入模式的每个分量，所有神经元使用相关的分量范数在距离评估过程中，使用存储在其中的对应的原型分量执行基本（或部分）距离计算。 然后使用“距离”范数组合距离基本计算，以确定输入模式和存储在神经元中的原型之间的最终距离。 在另一个实施例中，组件规范的集合被存储在原型存储装置中的神经元本身中，使得全局存储器不再是物理上必需的。 当ANN集成在硅芯片中时，该实现允许显着优化消耗的硅面积。

公开(公告)号：US06748405B2

公开(公告)日：2004-06-08

申请号：US09754639

申请日：2001-01-04

Applicant: Ghislain Imbert de Tremiolles ,  Didier Louis ,  Pascal Tannhof

Inventor： Ghislain Imbert de Tremiolles ,  Didier Louis ,  Pascal Tannhof

IPC: G06F700

CPC classification number: G06F7/544 ,  G06F7/22 ,  G06F9/30021

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=K×n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a “thermometric” coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.

Abstract translation: 在搜索在q位上编码的p个编码集合中的最小值时，每个数字被分割为以n位编码的K个子值（q> = Kxn）。 因此，参数K为每个子值分配等级，使得形成K个比特片，其中每个切片由相同等级的子值组成。 然后使用“温度测量”编码技术，以m位（m> n）对每个子值进行编码。 然后对编码子值（MSB）的第一切片执行并行搜索以确定该切片的最小子值。 所有与子值相关联的数字大于已评估的最小子值的数字将被取消选择。 评估过程以相同的方式继续，直到最后一个切片（LSB）被处理。 在评估过程结束时，保持选中的数字具有最小值。 响应时间（即处理步骤的数目）现在只取决于数字已被分割的子值的数量K. 该方法也适用于搜索最大值。

公开(公告)号：US06622135B1

公开(公告)日：2003-09-16

申请号：US09465088

申请日：1999-12-16

Applicant: Gislain Imbert De Tremiolles ,  Pascal Tannhof ,  Erin Williams

Inventor： Gislain Imbert De Tremiolles ,  Pascal Tannhof ,  Erin Williams

IPC: G06N306

CPC classification number: G06K9/6276 ,  G06T7/0004 ,  G06T2207/30148

Abstract: To avoid the problem of category assignment in artificial neural networks (ANNs) based upon a mapping of the input space (like ROI and KNN algorithms), the present method uses “probabilities”. Now patterns memorized as prototypes do not represent categories any longer but the “probabilities” to belong to categories. Thus, after having memorized the most representative patterns in a first step of the learning phase, the second step consists of an evaluation of these probabilities. To that end, several counters are associated with each prototype and are used to evaluate the response frequency and accuracy for each neuron of the ANN. These counters are dynamically incremented during this second step using distances evaluation (between the input vectors and the prototypes) and error criteria (for example the differences between the desired responses and the response given by the ANN). At the end of the learning phase, a function of the contents of these counters allows an evaluation of these probabilities for each neuron to belong to predetermined categories. During the recognition phase, the probabilities associated with the neurons selected by the algorithm permit the characterization of new input vectors and more generally any kind of input (images, signals, sets of data) to detect and classify anomalies. The method allows a significant reduction in the number of neurons that are required in the ANN while improving its overall response accuracy.

Abstract translation: 为了避免基于输入空间（如ROI和KNN算法）的映射的人造神经网络（ANN）中的类别分配问题，本方法使用“概率”。 现在存储为原型的图案不再代表类别，而是属于类别的“概率”。 因此，在学习阶段的第一步中记住最具代表性的模式之后，第二步包括这些概率的评估。 为此，几个计数器与每个原型相关联，并用于评估ANN的每个神经元的响应频率和精度。 这些计数器在第二步使用距离评估（输入向量和原型之间）和错误标准（例如期望响应与ANN给出的响应之间的差异）进行动态递增。 在学习阶段结束时，这些计数器的内容的功能允许将每个神经元的这些概率的评估属于预定类别。 在识别阶段，与算法选择的神经元相关联的概率允许表征新的输入向量，更一般地，可以检测和分类异常的任何种类的输入（图像，信号，数据集）。 该方法允许在ANN中需要的神经元数目显着减少，同时提高其整体响应精度。

公开(公告)号：US06523018B1

公开(公告)日：2003-02-18

申请号：US09470459

申请日：1999-12-22

Applicant: Didier Louis ,  Pascal Tannhof ,  André Steimle

Inventor： Didier Louis ,  Pascal Tannhof ,  André Steimle

IPC: G06N306

CPC classification number: G06K9/6276 ,  G06N3/063

Abstract: The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the feed back and control signals. The R/W memory block, typically a RAM, is common to all neurons to avoid circuit duplication, increasing thereby the number of neurons integrated in the chip. The R/W memory stores the prototype components. Each neuron comprises a computation block, a register block, an evaluation block and a daisy chain block to chain the neurons. All these blocks (except the computation block) have a symmetric structure and are designed so that each neuron may operate in a dual manner, i.e. either as a single neuron (single mode) or as two independent neurons (dual mode). Each neuron generates local signals. The neural chip further includes an OR circuit which performs an OR function for all corresponding local signals to generate global signals that are merged in an on-chip common communication bus shared by all neurons of the chip. The R/W memory block, the neurons and the OR circuit form an artificial neural network having high flexibility due to this dual mode feature which allows to mix single and dual neurons in the ANN.

Abstract translation: 神经半导体芯片首先包括：全局寄存器和控制逻辑电路块，R / W存储器块和由传送诸如输入向量数据，建立参数等的数据的总线馈送的多个神经元，以及诸如 作为反馈和控制信号。 R / W存储器块（通常为RAM）对于所有神经元是共同的，以避免电路重复，从而增加集成在芯片中的神经元的数量。 R / W存储器存储原型组件。 每个神经元包括计算块，寄存器块，评估块和菊花链块以链接神经元。 所有这些块（计算块除外）具有对称结构，并且被设计成使得每个神经元可以以双重方式操作，即作为单个神经元（单个模式）或两个独立神经元（双模式）操作。 每个神经元产生本地信号。 所述神经芯片还包括OR电路，其对所有相应的本地信号执行OR功能，以产生合并在由所述芯片的所有神经元共享的片上公共通信总线中的全局信号。 R / W存储器块，神经元和OR电路形成具有高灵活性的人造神经网络，由于这种双模式特征，其允许在ANN中混合单个和双重神经元。