公开(公告)号：US07328397B2

公开(公告)日：2008-02-05

申请号：US10805168

申请日：2004-03-19

Applicant: Massimiliano Lunelli ,  Rino Micheloni ,  Roberto Ravasio ,  Alessia Marelli

Inventor： Massimiliano Lunelli ,  Rino Micheloni ,  Roberto Ravasio ,  Alessia Marelli

IPC: H03M13/00

CPC classification number: H03M13/1575 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received.Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

公开(公告)号：US20070234164A1

公开(公告)日：2007-10-04

申请号：US11713376

申请日：2007-03-01

Applicant: Alessia Marelli ,  Valeria Intini ,  Roberto Ravasio ,  Rino Micheloni

Inventor： Alessia Marelli ,  Valeria Intini ,  Roberto Ravasio ,  Rino Micheloni

IPC: G06F11/00 ,  G01R31/28

CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS−1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

Abstract translation: 具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A 0，A 1，...，ALS-1）的第一读取以产生第一恢复串 S1），并且使用第一恢复串执行第一解码尝试（S1）。 当第一解码尝试失败时，至少读取一次存储器位置，并产生至少一个第二恢复字符串（S 2 -SN）。 基于第一恢复字符串（S 1）和第二恢复字符串（S 2 -SN）之间的比较，生成修饰字符串（SM），其中存在消息（X），并且至少一个第二 使用修改的串（SM）进行解码尝试。

公开(公告)号：US20070047299A1

公开(公告)日：2007-03-01

申请号：US11458904

申请日：2006-07-20

Applicant: Angelo Bovino ,  Vincenzo Altieri ,  Roberto Ravasio ,  Rino Micheloni ,  Mario De Matteis

Inventor： Angelo Bovino ,  Vincenzo Altieri ,  Roberto Ravasio ,  Rino Micheloni ,  Mario De Matteis

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C2211/5641

Abstract: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.

Abstract translation: 多级编程允许通过从第二位单独编程第一位来在选定单元中写入第一位和第二位。 第一位的编程确定从第一阈值电平转换到第二阈值电平。 第二位的编程需要初步读取以检测第一位是否已被修改，如果第一位已被修改并执行第二写入步骤，执行第一写入步骤以使单元进入第三阈值电压，以使所选择的 如果第一位未被修改，则将单元转换为不同于第三阈值电平的第四阈值电压。 为了增加读取和编程的可靠性，在第二部分的初步读取期间，读取结果被迫对应于第一阈值水平。

公开(公告)号：US20060285387A1

公开(公告)日：2006-12-21

申请号：US11445491

申请日：2006-05-31

Applicant: Rino Micheloni ,  Roberto Ravasio ,  Iiaria Motta

Inventor： Rino Micheloni ,  Roberto Ravasio ,  Iiaria Motta

IPC: G11C16/04

CPC classification number: G11C16/3404 ,  G11C16/3409

Abstract: A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.

Abstract translation: NAND闪速存储器件包括每个具有阈值电压的存储器单元矩阵。 矩阵包括单独的可擦除扇区，并且被布置成多行和列，其中每列的单元被排列成串联连接的多个单元格单元。 存储器件包括擦除所选扇区的单元的逻辑，以及恢复已擦除单元的阈值电压的恢复逻辑。 恢复逻辑依次作用于扇区的多个块中的每个块，每个块包括一个或多个单元的组。 恢复逻辑相对于超过读取参考值的极限值读取每个组，仅对至少一个单元的阈值电压未达到极限值的每个组进行编程，并响应于达到极限值而停止恢复 至少一组这些组。

公开(公告)号：US20050050434A1

公开(公告)日：2005-03-03

申请号：US10805168

申请日：2004-03-19

Applicant: Massimiliano Lunelli ,  Rlno Micheloni ,  Roberto Ravasio ,  Alessia Marelli

Inventor： Massimiliano Lunelli ,  Rlno Micheloni ,  Roberto Ravasio ,  Alessia Marelli

IPC: H03M13/13 ,  H03M13/15 ,  H03M13/19 ,  H03M13/00 ,  H03M13/03

CPC classification number: H03M13/1575 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

Abstract: A method for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, providing the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract translation: 描述了对编码为符号序列的数字信息进行错误校正的方法，例如存储在电子存储器系统中或从这些系统发送的数字信息或从这些系统发送和传送到这些系统的数字信息，提供包含错误校正码的一部分的序列的传输， 更可能的是，通过使用奇偶校验矩阵计算错误校正子来传送原始信息，以便在接收时恢复。 有利的是，根据本发明，并入原始序列中的错误代码属于非布尔组。

公开(公告)号：US07940575B2

公开(公告)日：2011-05-10

申请号：US12058191

申请日：2008-03-28

Applicant: Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

Inventor： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

IPC: G11C7/10 ,  G11C8/12 ,  G11C16/06

CPC classification number: G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

Abstract translation: 在一个实施例中，提供了一种用于在存储器件中传送数据的方法。 该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接 通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。 数据通过使用可控连接的逻辑连接进行传输。 同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

公开(公告)号：US07800943B2

公开(公告)日：2010-09-21

申请号：US12016750

申请日：2008-01-18

Applicant: Roberto Ravasio ,  Detlev Richter ,  Gert Koebernik ,  Girolamo Gallo ,  Mirko Reissmann ,  Ramirez Xavier Veredas

Inventor： Roberto Ravasio ,  Detlev Richter ,  Gert Koebernik ,  Girolamo Gallo ,  Mirko Reissmann ,  Ramirez Xavier Veredas

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/26 ,  B82Y10/00 ,  G11C5/02 ,  G11C5/04 ,  G11C11/5614 ,  G11C11/5642 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/004 ,  G11C13/025 ,  G11C16/0483 ,  G11C2013/0054 ,  G11C2211/5634 ,  G11C2213/16 ,  G11C2213/71

Abstract: Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.

Abstract translation: 本发明的实施例一般涉及具有存储单元布置的集成电路和使用多个部分读数来读取存储单元状态的方法。 在本发明的实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括至少一个存储单元，该存储单元能够存储可预定数量的存储单元阈值区分的多个存储单元状态，以及控制器，被配置为读取存储单元状态的存储单元状态 至少一个存储器单元，其使用高于所述预定数量的存储单元阈值的多个参考电平，其中所述读取包括使用第一组多个参考电平的第一部分读取和使用第二组的第二部分读取 多个参考电平的第二组，其中多个参考电平的第二组包括与多个参考电平的第一组的参考电平不同的至少一个参考电平。

公开(公告)号：US07730357B2

公开(公告)日：2010-06-01

申请号：US10805182

申请日：2004-03-19

Applicant: Rino Micheloni ,  Roberto Ravasio

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: G06F11/00

CPC classification number: G06F11/1068 ,  G06F11/1048

Abstract: An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

Abstract translation: 本发明的实施例涉及至少包括非易失性存储器和自动存储错误校正器的集成存储器系统，并且其中存储器通过接口总线连接到控制器。 有利地，该系统在存储器电路装置中包括功能上独立的，每个都负责校正预定的存储错误; 所述装置中的至少一个产生要求校正在存储器外部的信号。

公开(公告)号：US07719894B2

公开(公告)日：2010-05-18

申请号：US11828716

申请日：2007-07-26

Applicant: Luca Crippa ,  Roberto Ravasio ,  Rino Micheloni

Inventor： Luca Crippa ,  Roberto Ravasio ,  Rino Micheloni

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C7/18 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

Abstract translation: 可以利用NAND存储器件的两个相邻位线之间的电容耦合来升高不被编程的位线的电压，以便禁止对它们的编程操作。 包括不被编程的单元的偶数（奇数）位线用第一电压偏置，以阻止它们被编程，而包括要编程的单元的偶数（奇数）位线接地。 相邻的奇数（偶数）位线在电源电压或辅助电压处偏置，用于将偶数（奇数）位线的偏置电压升高到电源电压以上。 由于相邻位线之间的相关寄生耦合电容，包括不编程单元的偶数（奇数）位线的偏置电压会升高。

公开(公告)号：US20090244949A1

公开(公告)日：2009-10-01

申请号：US12058191

申请日：2008-03-28

Applicant: Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

Inventor： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

IPC: G11C5/06

CPC classification number: G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

Abstract translation: 在一个实施例中，提供了一种用于在存储器件中传送数据的方法。 该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接 通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。 数据通过使用可控连接的逻辑连接进行传输。 同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。