公开(公告)号：US12187600B2

公开(公告)日：2025-01-07

申请号：US17903473

申请日：2022-09-06

Applicant: STMicroelectronics S.r.l.

Inventor： Domenico Giusti ,  Carla Maria Lazzari

IPC: H01L41/04 ,  B81B3/00 ,  F04B43/04

Abstract: A MEMS actuator includes a semiconductor body with a first surface defining a housing cavity facing the first surface and having a bottom surface, the semiconductor body further defining a fluidic channel in the semiconductor body with a first end across the bottom surface. A strainable structure extends into the housing cavity, is coupled to the semiconductor body at the bottom surface, and defines an internal space facing the first end of the fluidic channel and includes at least a first and a second internal subspace connected to each other and to the fluidic channel. When a fluid is pumped through the fluidic channel into the internal space, the first and second internal subspaces expand, thereby straining the strainable structure along the first axis and generating an actuation force exerted by the strainable structure along the first axis, in an opposite direction with respect to the housing cavity.

公开(公告)号：US20250008847A1

公开(公告)日：2025-01-02

申请号：US18884913

申请日：2024-09-13

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Massimo Borghi

IPC: H10N70/20 ,  G11C13/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00

Abstract: A phase-change memory (PCM) includes a semiconductor body housing a selection transistor; a electrical-insulation body disposed over the semiconductor body; a conductive region, extending through the electrical-insulation body, electrically coupled to the selection transistor; and a plurality of heater elements in the electrical-insulation body. Each of the plurality of heater elements include a first end in electrical contact with a respective portion of the conductive region and a second end that extends away from the conductive region. The PCM further includes a plurality of phase-change elements extending in the electrical-insulation body and including data storage regions, where each of the data storage regions being electrically and thermally coupled to one respective heater element at the second end of the respective heater element.

公开(公告)号：US12175024B2

公开(公告)日：2024-12-24

申请号：US18048360

申请日：2022-10-20

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Paolo Rivolta ,  Federico Rizzardini

IPC: G06F3/0346 ,  G06F3/0354

Abstract: A method includes receiving electrostatic sensor data in a processor of an electronic device from an electrostatic sensor mounted behind a touchscreen of the electronic device and using the electrostatic sensor data to determine when the touchscreen is being used. Based on whether or not the touchscreen is being used, an on-table detection (OTD) algorithm is selected from a plurality of available OTD algorithms. In one or more examples, the OTD algorithm may also be selected based on the current device mode of the electronic device, which may be determined from a lid angle, a screen angle, and a keyboard angle of the electronic device. The selected OTD algorithm is run to determine whether or not the electronic device is located on a stationary or stable surface.

公开(公告)号：US12165880B2

公开(公告)日：2024-12-10

申请号：US17550747

申请日：2021-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Michele Derai

IPC: H01L21/48 ,  H01L21/78 ,  H01L23/495

Abstract: A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.

公开(公告)号：US12165871B2

公开(公告)日：2024-12-10

申请号：US17083181

申请日：2020-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando Iucolano ,  Cristina Tringali

IPC: H01L29/778 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66

Abstract: A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

公开(公告)号：US12164705B2

公开(公告)日：2024-12-10

申请号：US18059214

申请日：2022-11-28

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Federico Rizzardini ,  Lorenzo Bracco

IPC: G01B7/30 ,  G06F3/0346

Abstract: A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation: estimates an angular rate of change and determines a rotational versor based on the rotational data; and estimates a gravity vector based on the angular rate of change and the rotational versor. The processing circuitry generates a dynamic gravity vector based on the estimated gravity vector, a correction factor and an estimated error in estimated gravity vector. The processing circuitry estimates a linear acceleration and determines an acceleration versor based on the acceleration data, and determines the correction factor based on the linear acceleration. The processing circuitry estimates the error in the estimated gravity vector based on the acceleration versor.

公开(公告)号：US12164000B2

公开(公告)日：2024-12-10

申请号：US17460657

申请日：2021-08-30

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Cannone ,  Enrico Ferrara ,  Nicola Errico ,  Gea Donzelli

IPC: G01R31/3167 ,  G01R31/28 ,  G01R31/317

Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

公开(公告)号：US20240395680A1

公开(公告)日：2024-11-28

申请号：US18797031

申请日：2024-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Paolo CREMA

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A substrate of a lead frame is made of a first material. The substrate is covered by a barrier film made of a second material, different from the first material. The barrier film is then covered by a further film made of the first material. A first portion of the lead frame is encapsulated within an encapsulating body in a way which leaves a second portion of lead frame extending out from and not being covered by the encapsulating body. A first portion of the further film which is not covered by the encapsulating body is then stripped away to expose the barrier film at the second portion of the lead frame. A second portion of the further film is left remaining encapsulated by the encapsulating body. The exposed barrier film at the second portion of the lead frame is then covered with a tin or tin-based layer.

公开(公告)号：US12156303B2

公开(公告)日：2024-11-26

申请号：US17888214

申请日：2022-08-15

Applicant: STMicroelectronics S.r.l.

Inventor： Claudio Adragna ,  Giovanni Gritti

IPC: H05B45/10 ,  H02M1/42 ,  H05B45/385

Abstract: A control circuit includes: a flip-flop having an output configured to be coupled to a control terminal of a transistor and for producing a first signal; a comparator having an output coupled to an input of the flip-flop, and first and second inputs for receiving first and second voltages, respectively; a transconductance amplifier having an input for receiving a sense voltage indicative of a current flowing through the transistor, and an output coupled to the first input of the comparator; a zero crossing detection (ZCD) circuit having an input configured to be coupled to a first current path terminal of the transistor and to an inductor, where the ZCD circuit is configured to detect a demagnetization time of the inductor and produce a third signal based on the detected demagnetization time; and a reference generator configured to generate the second voltage based on the first and third signals.

公开(公告)号：US12148473B2

公开(公告)日：2024-11-19

申请号：US17697846

申请日：2022-03-17

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Roberto Bregoli ,  Vikas Rana

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B41/35 ,  H10B41/70

Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.