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公开(公告)号：US12051731B2
公开(公告)日：2024-07-30
申请号：US17698986
申请日：2022-03-18
IPC分类号： H01L29/16 , H01L27/06 , H01L29/423 , H01L29/872
CPC分类号： H01L29/4234 , H01L27/0629 , H01L29/1608 , H01L29/872
摘要： An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.
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22.发明公开公开(公告)号：US20240249955A1
公开(公告)日：2024-07-25
申请号：US18624589
申请日：2024-04-02
发明人： Paolo CREMA
IPC分类号： H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495
CPC分类号： H01L21/4842 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L23/49575
摘要： An multi-die semiconductor device disclosed herein includes a metallic leadframe with a central die pad encircled by electrically-conductive leads. Mounted on the die pad are two semiconductor dice, each with dedicated bonding pads on the surfaces facing away from the die pad. A layer of laser-activatable material is precisely molded over the dice and the leadframe. This layer forms a network of laser-activated lines: the first subset establishes electrical connections between the dice bonding pads and the leadframe leads, while the second subset interconnects the bonding pads of the first die to those of the second. There are two distinct metallic layers; the lower one, directly on the laser-activated lines, is formed of electroless-plated material, and the upper one, enhancing the structure, is formed of electroplated material, thus providing robust and reliable interconnections within the device.
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23.发明公开公开(公告)号：US20240231510A9
公开(公告)日：2024-07-11
申请号：US18048360
申请日：2022-10-20
IPC分类号： G06F3/0346 , G06F3/0354
CPC分类号： G06F3/0346 , G06F3/03547
摘要： A method includes receiving electrostatic sensor data in a processor of an electronic device from an electrostatic sensor mounted behind a touchscreen of the electronic device and using the electrostatic sensor data to determine when the touchscreen is being used. Based on whether or not the touchscreen is being used, an on-table detection (OTD) algorithm is selected from a plurality of available OTD algorithms. In one or more examples, the OTD algorithm may also be selected based on the current device mode of the electronic device, which may be determined from a lid angle, a screen angle, and a keyboard angle of the electronic device. The selected OTD algorithm is run to determine whether or not the electronic device is located on a stationary or stable surface.
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公开(公告)号：US20240230596A9
公开(公告)日：2024-07-11
申请号：US18489737
申请日：2023-10-18
发明人： Domenico GIUSTI , Marco DEL SARTO , Fabio QUAGLIA , Enri DUQI
CPC分类号： G01N29/04 , G01N29/2406 , G01N29/2437 , G01N2291/0231 , G01N2291/0289 , G01N2291/106
摘要： An integrated electronic system is provided with a package formed by a support base and a coating region arranged on the support base and having at least a first system die, including semiconductor material, coupled to the support base and arranged in the coating region. The integrated electronic system also has, within the package, a monitoring system configured to determine the onset of defects within the coating region, through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.
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公开(公告)号：US12033926B2
公开(公告)日：2024-07-09
申请号：US17498328
申请日：2021-10-11
IPC分类号： H01L23/00 , H01L21/48 , H01L21/768 , H01L23/31 , H01L23/498 , H01L21/60
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/76894 , H01L23/3135 , H01L23/49861 , H01L24/13 , H01L2021/60112 , H01L2224/13
摘要： A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.
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公开(公告)号：US12033663B2
公开(公告)日：2024-07-09
申请号：US18343868
申请日：2023-06-29
发明人： Ezio Galbiati
CPC分类号： G11B21/025 , G11B25/043 , G11B27/36 , G11B2220/2516
摘要： A circuit includes a set of input nodes configured to be coupled to respective ones of the windings of a spindle motor in a hard disk drive to sense the voltages applied to the windings. A set of output nodes is configured to provide output signals indicative of direction of flow of the currents through the windings. Level shifters are coupled to respective input nodes in the set of input nodes and have level-shifted output nodes configured to provide down-shifted replicas of the voltages at the respective input nodes in the set of input nodes. Flip-flops have inputs coupled to respective ones of the level-shifted output nodes of the level shifters and outputs configured to provide the output signals coupled to respective output nodes.
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27.发明公开公开(公告)号：US20240220777A1
公开(公告)日：2024-07-04
申请号：US18176315
申请日：2023-02-28
IPC分类号： G06N3/0464
CPC分类号： G06N3/0464
摘要： A hardware accelerator includes functional circuits and streaming engines. An interface is coupled to the plurality of streaming engines. The interface, in operation, performs stream cipher operations on data words associated with data streaming requests. The performing of a stream cipher operation on a data word includes generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines and an address associated with the data word, and XORing the generated mask with the data word. The hardware accelerator may include configuration registers to store configuration information indicating a respective security state associated with functional circuits and streaming engine of the hardware accelerator, which may be used to control performance of operations by the hardware accelerator.
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公开(公告)号：US12027964B2
公开(公告)日：2024-07-02
申请号：US18364811
申请日：2023-08-03
发明人： Maurizio Ricci , Marco Sautto , Simone Bellisai , Eleonora Chiaramonte , Luigi Arpini , Davide Betta
CPC分类号： H02M1/008 , H02M1/0025 , H02M3/156 , H02M3/157 , H02M3/158 , H02M1/0003
摘要： An embodiment circuit comprises first and second output nodes with an inductor arranged therebetween, and first and second switches coupled to opposing ends of the inductor. The switches are switchable between non-conductive and conductive states to control current flow through the inductor and produce first and second output voltages. The current intensity through the inductor is compared with at least one reference value. Switching control circuitry is coupled with the first and second switches, the first and second output nodes, and current sensing circuitry, which is configured to control the switching frequency of the first and second switches as a function of the output voltages and a comparison at the current sensing circuitry. The switching control circuitry is configured to apply FLL-FFWD processing to produce the reference values as a function of a timing signal, targeting maintaining a constant target value for the converter switching frequency.
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29.发明公开公开(公告)号：US20240212751A1
公开(公告)日：2024-06-27
申请号：US18543847
申请日：2023-12-18
CPC分类号： G11C13/004 , G06F17/16 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C2213/79
摘要： A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.
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公开(公告)号：US12021476B2
公开(公告)日：2024-06-25
申请号：US17514832
申请日：2021-10-29
发明人： Enrico Poli , Vincenzo Marano
IPC分类号： H02P7/29
CPC分类号： H02P7/29
摘要： A method and apparatus for adaptive rectification for preventing current inversion in motor windings are provided. In the method and apparatus, first and second half bridges of a plurality of half bridges are operated to synchronously rectify and permit passage of current, through the windings of the motor, in a first direction. A change of direction of the current from the first direction to a second direction opposite the first direction is detected. In response to detecting that the current changed direction to the second direction, the first and second half bridges of the plurality of half bridges are operated to quasi-synchronously rectify and block passage of the current through the windings in the second direction.
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