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公开(公告)号：US07176740B2
公开(公告)日：2007-02-13
申请号：US10948524
申请日：2004-09-24
申请人： Suguru Tachibana , Tatsuo Kato
发明人： Suguru Tachibana , Tatsuo Kato
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K17/102 , H03K17/223
摘要： A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.
摘要翻译： 电平转换电路，在适当进行电平转换的同时，防止电源电压下降时的运转速度降低。 电平转换电路包括第一和第二PMOS晶体管。 第一NMOS晶体管连接到第一PMOS晶体管和第二PMOS晶体管。 第二NMOS晶体管连接到第二PMOS晶体管和第一PMOS晶体管。 连接到第一和第二NMOS晶体管的偏置电路产生提供给第一和第二NMOS晶体管并且大于第一电压的第一和第二NMOS晶体管的阈值电压的偏置电位。 偏置电路还根据具有第一电压的控制信号控制电流，该电流确定偏置电位并流向偏置电路。
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公开(公告)号：US20050237099A1
公开(公告)日：2005-10-27
申请号：US10948524
申请日：2004-09-24
申请人： Suguru Tachibana , Tatsuo Kato
发明人： Suguru Tachibana , Tatsuo Kato
CPC分类号： H03K3/356113 , H03K17/102 , H03K17/223
摘要： A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.
摘要翻译： 电平转换电路，在适当进行电平转换的同时，防止电源电压下降时的运转速度降低。 电平转换电路包括第一和第二PMOS晶体管。 第一NMOS晶体管连接到第一PMOS晶体管和第二PMOS晶体管。 第二NMOS晶体管连接到第二PMOS晶体管和第一PMOS晶体管。 连接到第一和第二NMOS晶体管的偏置电路产生提供给第一和第二NMOS晶体管并且大于第一电压的第一和第二NMOS晶体管的阈值电压的偏置电位。 偏置电路还根据具有第一电压的控制信号控制电流，该电流确定偏置电位并流向偏置电路。
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公开(公告)号：US20050052303A1
公开(公告)日：2005-03-10
申请号：US10774525
申请日：2004-02-10
申请人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
发明人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
摘要： An AD converter includes a sample-&-hold circuit which samples and holds an input analog potential in a first period, and generates a signal indicative of a magnitude relation between the held input analog potential and a reference potential in a second period, a plurality of amplifiers connected in series which amplify an output of the sample-&-hold circuit, and a control circuit which controls operating timing of the amplifiers so as to make at least one of the amplifiers start operating in a middle of the first period.
摘要翻译： AD转换器包括采样保持电路，其在第一周期中采样并保持输入模拟电位，并且产生指示在第二周期中保持的输入模拟电位与参考电位之间的大小关系的信号，多个 放大器连接的放大器，其放大采样保持电路的输出;以及控制电路，其控制放大器的工作时序，以使至少一个放大器在第一周期的中间开始工作。
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公开(公告)号：US6121646A
公开(公告)日：2000-09-19
申请号：US913407
申请日：1997-12-05
CPC分类号： G11C11/5621 , G11C15/04
摘要： A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.
摘要翻译： PCT No.PCT / JP96 / 00701 Sec。 371 1997年12月5日第 102（e）日期1997年12月5日PCT 1996年3月18日PCT公布。 出版物WO96 / 29705 日期1996年9月26日一种半导体集成电路，特别是用于安装在微处理器LSI中的高速低功耗表格旁路缓冲器的电路。 半导体集成电路设置有用于将输入的多位数据信号与存储的数据进行比较的场效应晶体管和至少在数据信号与存储的数据进行比较时施加电流的符合检测信号线（25）。 当数据信号与存储的数据一致时，晶体管（26）导通。 晶体管（26）的数量等于输入的数据信号的数量。 晶体管的漏极（260）并联连接，源极并联连接并以预定电压供电，通过集成电路，通过检测电位来检测输入的数据信号是否与存储的数据一致 的一致检测信号线（25）。
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公开(公告)号：US5218567A
公开(公告)日：1993-06-08
申请号：US789003
申请日：1991-11-07
CPC分类号： G06F12/1054 , G06F12/0895 , G11C15/04
摘要： A cache memory apparatus made up of a memory cell array (300) and a match detection circuit is disclosed. The match detection circuit produces a detection signal related to whether a search data coincides with a data read out of the memory cell array (300). The match detection circuit applies complementary signals (d, d) of the data read from the memory cell array (300) to the bases of bipolar differential transistors (10, 11), the gates of a pair of field effect transistors (16, 17) are supplied with complementary signals (a, a) of the search data, and the bases of a pair of emitter-follower transistors (12, 13) are connected to the collectors of the bipolar differential transistors (10, 11), thereby producing a detection signal (HITO) from the jointly-connected emitters thereof.
摘要翻译： 公开了一种由存储单元阵列（300）和匹配检测电路构成的高速缓存存储装置。 匹配检测电路产生与搜索数据是否与从存储单元阵列（300）读出的数据一致的检测信号。 匹配检测电路将从存储单元阵列（300）读取的数据的互补信号（d，＆amp; upbar＆d）施加到双极差分晶体管（10,11）的基极，一对场效应晶体管（16， 17）被提供有搜索数据的互补信号（a，＆amp; upbar＆a），并且一对射极跟随器晶体管（12,13）的基极连接到双极差分晶体管（10,11）的集电极， 从而从其共同连接的发射器产生检测信号（＆amp; upbar＆amp; H）。
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公开(公告)号：US4928265A
公开(公告)日：1990-05-22
申请号：US266148
申请日：1988-11-02
IPC分类号： G11C11/416
CPC分类号： G11C11/416
摘要： Considering the dispersion in the access time of semiconductor memories, at least a first and a second memory circuit are connected to the output of a sense amplifier. The output of the sense amplifier is an input to these two memory circuits alternatively at different timings. The data stored in these memory circuits are alternately transferred to a data output circuit. Even when the access time becomes long, the desired sense data can be successively read out from the output of the data output circuit at a short time interval determined by the clock cycle. When the access time becomes short and even when a second data is generated from the output of the sense amplifier at the timing of transferring a first data in the first memory circuit to the data output circuit, the first data held in the first memory circuit is prevented from being renewed by the second data. In this case too, the desired sense data can be successively read out from the output of the data output circuit at a time interval determined by the clock cycle.
摘要翻译： 考虑到半导体存储器的访问时间的偏差，至少第一和第二存储器电路连接到读出放大器的输出。 读出放大器的输出是以不同的定时交替地输入到这两个存储器电路。 存储在这些存储器电路中的数据被交替地传送到数据输出电路。 即使当访问时间变长时，可以在由时钟周期确定的短时间间隔内从数据输出电路的输出端连续地读出期望的感测数据。 当访问时间变短时，即使在将第一存储器电路中的第一数据传送到数据输出电路的定时从读出放大器的输出产生第二数据时，保持在第一存储器电路中的第一数据为 防止第二个数据被更新。 在这种情况下，也可以在由时钟周期确定的时间间隔内从数据输出电路的输出端连续读出期望的检测数据。
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公开(公告)号：US20120212194A1
公开(公告)日：2012-08-23
申请号：US13316522
申请日：2011-12-11
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A reference voltage circuit includes a first amplifier, a first load device and a first PN junction device, second and third load devices and a second PN junction device, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit. The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier, and the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes. The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.
摘要翻译： 参考电压电路包括第一放大器，第一负载装置和第一PN结装置，第二和第三负载装置和第二PN结装置，偏移电压降低电路，耦合节点势能取出电路和区域调整电路 。 偏移电压降低电路被配置为减少第一放大器处的第一和第二输入端之间的偏移电压，并且耦合节点电势取出电路被配置为取出第一和第二耦合节点的电位。 区域调整电路被配置为根据由耦合节点电势取出电路取出的第一和第二耦合节点的电位来调整第二PN结装置的面积。
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公开(公告)号：US20110316515A1
公开(公告)日：2011-12-29
申请号：US13158054
申请日：2011-06-10
申请人： Kazuhiro MITSUDA , Koji Okada , Suguru Tachibana
发明人： Kazuhiro MITSUDA , Koji Okada , Suguru Tachibana
IPC分类号： G05F3/02
摘要： An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.
摘要翻译： 一种包括参考电压产生电路的振荡电路，其将与绝对温度成比例增加的比例绝对温度（PTAT）输出添加到互补绝对温度（CTAT）输出，其降低 与绝对温度成比例，以产生和输出参考电压。 振荡电路产生具有期望和固定频率的振荡信号。
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公开(公告)号：US20100156533A1
公开(公告)日：2010-06-24
申请号：US12535184
申请日：2009-08-04
申请人： Suguru Tachibana , Kenta Aruga , Tatsuo Kato
发明人： Suguru Tachibana , Kenta Aruga , Tatsuo Kato
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/347 , H03F3/45183 , H03F2200/453 , H03F2200/456 , H03F2203/45138 , H03F2203/45466
摘要： The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.
摘要翻译： 本发明被设计为采用差分对型放大器电路，其包括由接收第一信号的输入的第一晶体管和由第二晶体管构成的差分对，所述第二晶体管接收通过输出第二信号而产生的第三信号的输入， 电压电平是电源电压。 需要匹配的元件是构成放大器电路的差分对的两个晶体管。 因此，不管放大器电路之间的布局如何，需要匹配的元件可以彼此靠近放置。
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公开(公告)号：US07642945B2
公开(公告)日：2010-01-05
申请号：US12035899
申请日：2008-02-22
申请人： Suguru Tachibana , Ikuo Hiraishi , Azusa Saito
发明人： Suguru Tachibana , Ikuo Hiraishi , Azusa Saito
IPC分类号： H03M1/34
CPC分类号： H03M1/462
摘要： A successive approximation type AD converter circuit for comparing an analog input signal with an output analog signal of a DA converter with a comparator to input a digital signal output in accordance with a comparison result to the DA converter to determine a digital signal obtained if the output analog signal of the DA converter is equal to the analog input signal, as an AD-converted output signal, includes: an AD converter for AD-converting the analog input circuit in accordance with a sampling period for sampling the analog input signal and a comparison period for comparing the sampled analog input signal with the output analog signal of the DA converter with the comparator; and setting means for independently setting a cycle time of a first clock signal for determining the sampling period and a cycle time of a second clock signal for determining the comparison period.
摘要翻译： 一种逐次逼近型AD转换器电路，用于将模拟输入信号与DA转换器的输出模拟信号与比较器进行比较，以将根据比较结果输出的数字信号输入到DA转换器，以确定如果输出 DA转换器的模拟信号等于模拟输入信号，作为AD转换的输出信号，包括：AD转换器，用于根据用于对模拟输入信号进行采样的采样周期对模拟输入电路进行AD转换，并进行比较 将采样的模拟输入信号与DA转换器的输出模拟信号与比较器进行比较的周期; 以及用于独立地设置用于确定采样周期的第一时钟信号的周期时间和用于确定比较周期的第二时钟信号的周期时间的设置装置。
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